Stem rtl$ (all stems)

78 papers:

DAC-2015-EspinosaHAAR #analysis #correlation #robust #set #verification

Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification (JE, CH, JA, DdA, JCR), p. 6.

DATE-2015-BombieriFPS #abstraction #verification

RTL property abstraction for TLM assertion-based verification (NB, RF, GP, FS), pp. 85–90.

DAC-2014-AthavaleMHV #analysis #source code #test coverage #using

Code Coverage of Assertions Using RTL Source Code Analysis (VA, SM, SH, SV), p. 6.

DATE-2014-PapadimitriouHBML #clustering #fault #injection #modelling #multi #towards

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks (AP, DH, VB, PM, RL), pp. 1–4.

DATE-2014-SinghSWPWC #analysis #specification

Cross-correlation of specification and RTL for soft IP analysis (BPS, AS, FGW, CAP, DJW, SC), pp. 1–6.

DAC-2013-BombieriLFC #c++ #synthesis

A method to abstract RTL IP blocks into C++ code and enable high-level synthesis (NB, HYL, FF, LPC), p. 9.

DATE-2013-HeLLHY #streaming #synthesis

Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications (XH, SL, YL, XSH, HY), pp. 992–995.

DAC-2012-KumarBKV #analysis #predict #source code #using

Early prediction of NBTI effects using RTL source code analysis (JAK, KMB, HK, SV), pp. 808–813.

DAC-2012-UrdahlSWK #abstraction #composition #concurrent #verification

System verification of concurrent RTL modules by compositional path predicate abstraction (JU, DS, MW, WK), pp. 334–343.

DATE-2012-BombieriFG #fault #framework #functional #named #simulation #verification

FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs (NB, FF, VG), pp. 562–565.

DATE-2012-ChangCM #analysis

RTL analysis and modifications for improving at-speed test (KHC, HZC, ILM), pp. 400–405.

DATE-2012-VyagrheswaruduDR #framework #interactive #named #optimisation

PowerAdviser: An RTL power platform for interactive sequential optimizations (NV, SD, AR), pp. 550–553.

TACAS-2012-YehWH #design #framework #named #open source #synthesis #towards #verification

QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification (HHY, CYW, CY(H), pp. 377–391.

DATE-2011-LiuV #analysis #generative #performance #source code #validation

Efficient validation input generation in RTL by hybridized source code analysis (LL, SV), pp. 1596–1601.

DAC-2010-BombieriFP #abstraction #embedded

Abstraction of RTL IPs into embedded software (NB, FF, GP), pp. 24–29.

DATE-2010-ChouYCDK #case study #design #nondeterminism #scalability

Finding reset nondeterminism in RTL designs — scalable X-analysis methodology and case study (HZC, HY, KHC, DD, SYK), pp. 1494–1499.

DATE-2009-BombieriFPV #generative

Correct-by-construction generation of device drivers based on RTL testbenches (NB, FF, GP, SV), pp. 1500–1505.

DATE-2009-KoelblJJP #equivalence

Solver technology for system-level to RTL equivalence checking (AK, RJ, HJ, CP), pp. 196–201.

DAC-2008-Beers #experience #verification

Pre-RTL formal verification: an intel experience (RB), pp. 806–811.

DAC-2008-Ng #challenge #modelling #using #verification

Challenges in using system-level models for RTL verification (KN), pp. 812–815.

DAC-2008-UrardMGC #equivalence

Leveraging sequential equivalence checking to enable system-level to RTL flows (PU, AM, RG, NC), pp. 816–821.

DATE-2008-BombieriDF #automation #design #generative

Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation (NB, ND, FF), pp. 15–20.

DAC-2007-DengBWYZ #named #performance #satisfiability #using

EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure (SD, JB, WW, XY, YZ), pp. 588–593.

DAC-2007-KasuyaT #design #verification

Verification Methodologies in a TLM-to-RTL Design Flow (AK, TT), pp. 199–204.

DAC-2007-KoelblBP #equivalence #memory management #modelling

Memory Modeling in ESL-RTL Equivalence Checking (AK, JRB, CP), pp. 205–209.

DAC-2007-MathurK #design #modelling #verification

Design for Verification in System-level Models and RTL (AM, VK), pp. 193–198.

DATE-2007-BombieriFP #design #functional #incremental #refinement #validation

Incremental ABV for functional validation of TL-to-RTL design refinement (NB, FF, GP), pp. 882–887.

DATE-2007-KroeningS #image #interactive #proving #refinement #using #word

Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs (DK, NS), pp. 1325–1330.

DATE-2007-Naumann #design #evolution #question

Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore’s law? (AN), p. 2.

CAV-2007-Russinoff #approach #verification

A Mathematical Approach to RTL Verification (DMR), p. 2.

DAC-2006-BruceHNBRL #consistency #design #maintenance

Maintaining consistency between systemC and RTL system designs (ACB, MMKH, AN, SB, NR, CKL), pp. 85–89.

DAC-2006-FengH #equivalence #verification

Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification (XF, AJH), pp. 1063–1068.

DAC-2006-Swan #modelling #transaction #verification

SystemC transaction level models and RTL verification (SS), pp. 90–92.

DATE-2006-BombieriFP #evaluation #on the #reuse #verification

On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL (NB, FF, GP), pp. 1007–1012.

DATE-2006-ViswanathAJ #automation #pipes and filters #power management

Automatic insertion of low power annotations in RTL for pipelined microprocessors (VV, JAA, WAHJ), pp. 496–501.

DAC-2005-JainKSC #abstraction #refinement #verification #word

Word level predicate abstraction and refinement for verifying RTL verilog (HJ, DK, NS, EMC), pp. 445–450.

DAC-2005-ParthasarathyICB #learning

Structural search for RTL with predicate learning (GP, MKI, KTC, FB), pp. 451–456.

DATE-2005-IyerPC #constraints #learning #performance #theorem proving

Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver (MKI, GP, KTC), pp. 666–671.

DATE-2005-ZhaoG #semantics

Defining an Enhanced RTL Semantics (SZ, DDG), pp. 548–553.

DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation #synthesis

RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.

DATE-v1-2004-BabighianBM #algorithm #scalability

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks (PB, LB, EM), pp. 500–505.

DATE-v1-2004-BasuDDCMF #architecture #design #question #verification

Formal Verification Coverage: Are the RTL-Properties Covering the Design’s Architectural Intent? (PB, SD, PD, PPC, CRM, LF), pp. 668–669.

DATE-v1-2004-FernandesSOT #probability #testing

A Probabilistic Method for the Computation of Testability of RTL Constructs (JMF, MBS, ALO, JPT), pp. 176–181.

DATE-v1-2004-ReNR #automation #generative

A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters (ADR, AN, MR), pp. 686–687.

DATE-2005-FalconeriNR04 #modelling #reuse #verification

Common Reusable Verification Environment for BCA and RTL Models (GF, WN, NR), pp. 272–277.

DAC-2003-DonnoIBM #optimisation

Clock-tree power optimization based on RTL clock-gating (MD, AI, LB, EM), pp. 622–627.

DAC-2003-HsuTCT #debugging

Advanced techniques for RTL debugging (YCH, BT, YAC, FST), pp. 362–367.

DATE-2003-SantosFTT #generative #quality

RTL Test Pattern Generation for High Quality Loosely Deterministic BIST (MBS, JMF, ICT, JPT), pp. 10994–10999.

DATE-2003-WedlerSK #encoding #induction #using

Using RTL Statespace Information and State Encoding for Induction Based Property Checking (MW, DS, WK), pp. 11156–11157.

DAC-2002-SemeriaMPESN #concurrent #design #multi #thread #verification

RTL c-based methodology for designing and verifying a multi-threaded processor (LS, RM, BMP, AE, AS, DN), pp. 123–128.

DAC-2001-KolblKD #simulation

Symbolic RTL Simulation (AK, JHK, RFD), pp. 47–52.

DATE-2001-NicoliciA #3d #design #testing #trade-off

Testability trade-offs for BIST RTL data paths: the case for three dimensional design space (NN, BMAH), p. 802.

DATE-2001-ZengKC #approach #named #satisfiability

LPSAT: a unified approach to RTL satisfiability (ZZ, PK, MJC), pp. 398–402.

DATE-2001-Zhu #abstraction #design #named

MetaRTL: raising the abstraction level of RTL design (JZ), pp. 71–76.

CAV-2001-JohannsenB #design #named

BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction (PJ), pp. 373–377.

DAC-2000-GhoshF #automation #diagrams #functional #generative #using

Automatic test pattern generation for functional RTL circuits using assignment decision diagrams (IG, MF), pp. 43–48.

DAC-2000-HorstmannshoffM #code generation #data flow #graph #performance

Efficient building block based RTL code generation from synchronous data flow graphs (JH, HM), pp. 552–555.

DAC-1999-Bening #logic #simulation

A Two-State Methodology for RTL Logic Simulation (LB), pp. 672–677.

DAC-1999-BeniniMMOP #algorithm #approximate #component #kernel #optimisation

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms (LB, GDM, EM, GO, MP), pp. 247–252.

DAC-1999-MoussaSSDPCGJ #behaviour #design

Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper (IM, ZS, RS, MDN, MP, SC, LG, AAJ), pp. 598–603.

DATE-1999-MansouriV #design #verification

Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs (NM, RV), p. 223–?.

DATE-1999-PapachristouA #design #distributed

A Method of Distributed Controller Design for RTL Circuits (CAP, YA), pp. 774–775.

DAC-1998-GhoshJB #analysis #testing

A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis (IG, NKJ, SB), pp. 554–559.

DAC-1997-FangWY #debugging #online #realtime

A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications (WJF, ACHW, TYY), pp. 101–106.

DAC-1997-YimHPCYOPK #design #verification

A C-Based RTL Design Verification Methodology for Complex Microprocessor (JSY, YHH, CJP, HC, WSY, HSO, ICP, CMK), pp. 83–88.

EDTC-1997-BhattacharyaDS #testing

An RTL methodology to enable low overhead combinational testing (SB, SD, BS), pp. 146–152.

EDTC-1997-XuK #physics #synthesis

RTL synthesis with physical and controller information (MX, FJK), pp. 299–303.

DAC-1996-PapachristouSN #design #effectiveness #multi #power management

An Effective Power Management Scheme for RTL Design Based on Multiple Clocks (CAP, MS, MN), pp. 337–342.

DAC-1996-SawantG #verification

RTL Emulation: The Next Leap in System Verification (SS, PG), pp. 233–235.

CAV-1996-AnonBCCLSTXZ #design #tool support #verification

MDG Tools for the Verification of RTL Designs (KDA, NB, EC, FC, ML, XS, ST, YX, ZZ), pp. 433–436.

DAC-1995-ParulkarGB #design

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead (IP, SKG, MAB), pp. 395–401.

DAC-1994-PrasadAB #design #incremental #synthesis

A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes (SCP, PA, PWB), pp. 441–446.

FME-1994-WangM

RTL and Refutation by Positive Cycles (FW, AKM), pp. 659–680.

DAC-1993-NouraniP #algorithm #estimation #layout

A Layout Estimation Algorithm for RTL Datapaths (MN, CAP), pp. 285–291.

DAC-1991-DuttK #library #synthesis

Bridging High-Level Synthesis to RTL Technology Libraries (NDD, JRK), pp. 526–529.

CAV-1990-Langevin #automation #calculus #verification

Automated RTL Verification Based on Predicate Calculus (ML), pp. 116–125.

DAC-1989-RoyA #approach #novel #using #verification

A Novel Approach to Accurate Timing Verification Using RTL Descriptions (KR, JAA), pp. 638–641.

DAC-1974-Hasterlik #automation #design #named

RTL — The firmware Design Automation system (RLH), pp. 284–299.