14 papers:
DATE-2012-NasseryO- An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode (AN, SO), pp. 1084–1089.
- DATE-2008-EberleG #architecture #automation #communication #design #network #power management #scalability
- A scalable low-power digital communication network architecture and an automated design path for controlling the analog/RF part of SDR transceivers (WE, MG), pp. 710–715.
- DATE-2007-DabrowskiR #interactive
- Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique (JD, RR), pp. 719–724.
- DATE-2007-LinC #design
- Testable design for advanced serial-link transceivers (ML, KT(C), pp. 695–700.
- DATE-DF-2006-BarontiDKMRSSSV
- FlexRay transceiver in a 0.35 µm CMOS high-voltage technology (FB, PD, MK, RM, RR, RS, MS, RS, VV), pp. 201–205.
- DATE-2005-BlazquezLWGPC #architecture
- Direct Conversion Pulsed UWB Transceiver Architecture (RB, FSL, DDW, BPG, JP, AC), pp. 94–95.
- DATE-DF-2004-DiazS #physics
- Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit (JCD, MS), pp. 134–139.
- DATE-DF-2004-WortmannSM #architecture #performance
- A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core (AW, SS, MM), pp. 46–51.
- DATE-2003-AholaWS #design
- Bluetooth Transceiver Design with VHDL-AMS (RA, DW, MS), pp. 20268–20273.
- DATE-2003-CaldariCCMGOT #modelling
- SystemC Modeling of a Bluetooth Transceiver: Dynamic Management of Packet Type in a Noisy Channel (MC, MC, PC, GM, FDG, SO, CT), pp. 20214–20219.
- DATE-2001-VandersteenWRSDEB #estimation #multi #performance
- Efficient bit-error-rate estimation of multicarrier transceivers (GV, PW, YR, JS, SD, ME, IB), pp. 164–168.
DAC-2000-VandersteenWRDDEB #data flow #performance #simulation- A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers (GV, PW, YR, PD, SD, ME, IB), pp. 440–445.
- DATE-1999-WambacqDZEMB
- A Single-Package Solution for Wireless Transceivers (PW, SD, HZ, ME, HDM, IB), p. 425–?.
- DAC-1998-RaelRA #design
- Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver (JR, AR, AAA), pp. 44–49.
