An Efficient Delay Test Generation System for Combinational Logic Circuits
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Eun Sei Park, M. Ray Mercer
An Efficient Delay Test Generation System for Combinational Logic Circuits
DAC, 1990.

DAC 1990
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@inproceedings{DAC-1990-ParkM,
	author        = "Eun Sei Park and M. Ray Mercer",
	booktitle     = "{Proceedings of the 27th Design Automation Conference}",
	doi           = "10.1145/123186.123390",
	isbn          = "0-89791-363-9",
	pages         = "522--528",
	publisher     = "{IEEE Computer Society Press}",
	title         = "{An Efficient Delay Test Generation System for Combinational Logic Circuits}",
	year          = 1990,
}

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