BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
3 × France
7 × USA
Collaborated with:
R.Kapur K.M.Butler C.T.Glover D.E.Ross T.W.Williams J.Dworak E.S.Park T.E.Kirkland E.Schell B.Cobb B.Underwood S.P.Smith B.Brodk J.Wingfield R.K.Gaede S.Lee M.R.Grimaila R.B.Brashear N.Menezes C.Oh L.T.Pillage J.Liou L.Wang K.Cheng
Talks about:
test (9) fault (6) delay (5) effici (4) algorithm (3) topolog (3) generat (3) circuit (3) order (3) use (3)

Person: M. Ray Mercer

DBLP DBLP: Mercer:M=_Ray

Contributed to:

DATE v2 20042004
DAC 20022002
DATE 20022002
EDAC-ETC-EUROASIC 19941994
DAC 19921992
DAC 19911991
DAC 19901990
DAC 19891989
DAC 19881988
DAC 19871987
DAC 19851985

Wrote 16 papers:

DATE-v2-2004-DworakCWM #detection #fault
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects (JD, BC, JW, MRM), pp. 1066–1071.
DAC-2002-LiouWCDMKW #fault #multi #performance #testing #using
Enhancing test efficiency for delay fault testing using multiple-clocked schemes (JJL, LCW, KTC, JD, MRM, RK, TWW), pp. 371–374.
DATE-2002-KapurWM #logic
Directed-Binary Search in Logic BIST Diagnostics (RK, TWW, MRM), p. 1121.
DATE-2002-LeeCDGM #algorithm #detection #fault #multi #testing
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults (SL, BC, JD, MRG, MRM), pp. 94–99.
EDAC-1994-BrashearMOPM #analysis #performance #predict #statistics #using
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis (RBB, NM, CO, LTP, MRM), pp. 332–337.
DAC-1992-MercerKR #functional #generative #order #performance
Functional Approaches to Generating Orderings for Efficient Symbolic Representations (MRM, RK, DER), pp. 624–627.
DAC-1991-ButlerRKM #diagrams #heuristic #order #performance
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams (KMB, DER, RK, MRM), pp. 417–420.
DAC-1991-WilliamsUM #network #testing
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing (TWW, BU, MRM), pp. 87–92.
DAC-1990-ButlerM #design #fault #performance
The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design (KMB, MRM), pp. 673–678.
DAC-1990-ParkM #generative #logic #performance #testing
An Efficient Delay Test Generation System for Combinational Logic Circuits (ESP, MRM), pp. 522–528.
DAC-1989-GloverM #approach #fault #testing
A Deterministic Approach to Adjacency Testing for Delay Faults (CTG, MRM), pp. 351–356.
DAC-1988-GaedeRMB #automation #concurrent #named #parallel #testing #using
CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology (RKG, DER, MRM, KMB), pp. 597–600.
DAC-1988-GloverM #fault #generative #testing
A Method of Delay Fault Test Generation (CTG, MRM), pp. 90–95.
DAC-1987-KirklandM #algorithm
A Topological Search Algorithm for ATPG (TEK, MRM), pp. 502–508.
DAC-1987-SmithMB #simulation
Demand Driven Simulation: BACKSIM (SPS, MRM, BB), pp. 181–187.
DAC-1985-SchellM #algorithm #development #named
CADTOOLS: a CAD algorithm development system (ES, MRM), pp. 658–666.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.