Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks
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Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks
DATE, 1997.

EDTC 1997
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@inproceedings{EDTC-1997-BeniniMMPS,
	author        = "Luca Benini and Giovanni De Micheli and Enrico Macii and Massimo Poncino and Riccardo Scarsi",
	booktitle     = "{Proceedings of the Second European Design and Test Conference}",
	doi           = "10.1109/EDTC.1997.582409",
	pages         = "514--520",
	publisher     = "{IEEE}",
	title         = "{Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks}",
	year          = 1997,
}

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