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Travelled to:
2 × USA
Collaborated with:
M.W.Stebnisky M.J.McGinnis J.C.Werbickas R.Putatunda
Talks about:
automat (2) turnaround (1) synthesi (1) system (1) random (1) layout (1) custom (1) quick (1) logic (1) devic (1)

Person: A. Feller

DBLP DBLP: Feller:A=

Contributed to:

DAC 19831983
DAC 19761976

Wrote 2 papers:

DAC-1983-StebniskyMWPF #automation #named #synthesis
APSS: An automatic PLA synthesis system (MWS, MJM, JCW, RP, AF), pp. 430–435.
DAC-1976-Feller #automation #layout #low cost
Automatic layout of low-cost quick-turnaround random-logic custom LSI devices (AF), pp. 79–85.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.