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Travelled to:
1 × Canada
2 × France
8 × USA
Collaborated with:
V.Singhal A.Kölbl M.Kaufmann F.Somenzi J.R.Burch I.Moon P.Bjesse A.Martin J.Rho S.Jeong G.D.Hachtel R.Jacoby H.Jain J.Yuan K.Albin A.Aziz J.Jang S.Qadeer R.L.Rudell R.K.Brayton R.K.Gupta S.Rawat S.K.Shukla B.Bailey D.K.Beece M.Fujita J.O'Leary
Talks about:
equival (4) check (4) sequenti (3) verif (3) model (3) constraint (2) synchron (2) sequenc (2) circuit (2) formal (2)

Person: Carl Pixley

DBLP DBLP: Pixley:Carl

Contributed to:

DATE 20092009
DAC 20072007
DATE 20072007
DAC 20032003
CAV 19981998
DAC 19971997
DAC 19951995
CAV 19941994
DAC 19931993
DAC 19921992
CAV 19901990

Wrote 12 papers:

DATE-2009-KoelblJJP #equivalence
Solver technology for system-level to RTL equivalence checking (AK, RJ, HJ, CP), pp. 196–201.
DAC-2007-KoelblBP #equivalence #memory management #modelling
Memory Modeling in ESL-RTL Equivalence Checking (AK, JRB, CP), pp. 205–209.
DATE-2007-MoonBP #approach #composition #equivalence
A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states (IHM, PB, CP), pp. 1170–1175.
DAC-2003-GuptaRSBBFPOS #verification
Formal verification — prove it or pitch it (RKG, SR, SKS, BB, DKB, MF, CP, JO, FS), pp. 710–711.
DAC-2003-YuanAAP #constraints #functional #modelling #synthesis #verification
Constraint synthesis for environment modeling in functional verification (JY, KA, AA, CP), pp. 296–299.
CAV-1998-KaufmannMP #constraints #design #model checking
Design Constraints in Symbolic Model Checking (MK, AM, CP), pp. 477–487.
DAC-1997-JangQKP #case study #verification
Formal Verification of FIRE: A Case Study (JYJ, SQ, MK, CP), pp. 173–177.
The Validity of Retiming Sequential Circuits (VS, CP, RLR, RKB), pp. 316–321.
CAV-1994-SinghalP #problem
The Verifiacation Problem for Safe Replaceability (VS, CP), pp. 311–323.
DAC-1993-RhoSP #finite #sequence #state machine
Minimum Length Synchronizing Sequences of Finite State Machine (JKR, FS, CP), pp. 463–468.
DAC-1992-PixleyJH #diagrams #sequence
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams (CP, SWJ, GDH), pp. 620–623.
CAV-1990-Pixley #equivalence #hardware #implementation
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence (CP), pp. 54–64.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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