Travelled to:1 × France
1 × Germany
Collaborated with:M.Nicolaidis N.Zergainoh F.Chaix L.Anghel Y.Zorian T.Karnik K.A.Bowman J.Tschanz S.Lu C.Tokunaga A.Raychowdhury M.M.Khellah J.Kulkarni V.De
Talks about:interconnect (1) deadlock (1) reliabl (1) design (1) ultim (1) toler (1) fault (1) adapt (1) test (1) rout (1)
Person: Dimiter Avresky
DBLP: Avresky:Dimiter
Contributed to:
20122011Wrote 2 papers:
- DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability
- Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
- DATE-2011-ChaixAZN #adaptation #concurrent #fault tolerance
- A fault-tolerant deadlock-free adaptive routing for on chip interconnects (FC, DA, NEZ, MN), pp. 909–912.