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Travelled to:
5 × France
5 × Germany
7 × USA
Collaborated with:
N.Kranitis D.Gizopoulos A.M.Paschalis M.Nicolaidis E.J.Marinissen N.Mokhoff M.Renovell J.M.Portal J.Figueras M.Psarakis R.Wilson I.Pomeranz C.Dufaza D.Wassung A.J.v.d.Goor I.Schanstra K.N.Ruparel P.Muhmenthaler B.Prince D.Keitel-Schulz T.Bogue M.Gössel H.Jürgensen R.d.O.Duarte H.Bederr M.S.Abadir M.Bapst C.Harris G.Xenoulis M.Redford J.Sawicki P.Subramaniam C.Hou K.Michaels H.Nham F.Pessolano K.S.Kim D.Y.Lepejian C.W.H.Strolenberg K.Veelenturf B.Frerichs J.Ensel G.Stark M.Gianfagna S.Venkataraman R.Puri S.Griffith A.Oberai R.Madge G.Yeric W.Ng P.Prinetto J.P.Teixeira I.C.Teixeira C.E.Pereira O.P.Dias J.Semião W.Radermacher C.Metra G.A.Mojoli S.Pastore D.Salvi G.R.Sechi L.Anghel N.Zergainoh T.Karnik K.A.Bowman J.Tschanz S.Lu C.Tokunaga A.Raychowdhury M.M.Khellah J.Kulkarni V.De D.Avresky
Talks about:
test (16) embed (6) design (5) self (4) core (4) base (4) processor (3) softwar (3) effect (3) determinist (2)

Person: Yervant Zorian

DBLP DBLP: Zorian:Yervant

Contributed to:

DATE 20122012
DAC 20092009
DAC 20072007
DAC 20062006
DAC 20052005
DATE 20052005
DATE 20032003
DAC 20022002
DATE 20022002
DATE 20012001
DAC 20002000
DATE 20002000
DATE 19991999
DAC 19981998
DATE 19981998
ED&TC 19971997

Wrote 29 papers:

DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability
Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
DAC-2009-RedfordSSHZM #named #question
DFM: don’t care or competitive weapon? (MR, JS, PS, CH, YZ, KM), pp. 296–297.
Making Manufacturing Work For You (SV, RP, SG, AO, RM, GY, WN, YZ), pp. 107–108.
DAC-2006-MokhoffZ #trade-off
Tradeoffs and choices for emerging SoCs in high-end applications (NM, YZ), p. 273.
Decision-making for complex SoCs in consumer electronic products (RW, YZ), p. 173.
DAC-2005-MokhoffZRNPK #how
How to determine the necessity for emerging solutions (NM, YZ, KNR, HN, FP, KSK), pp. 274–275.
DAC-2005-WassungZABH #design
Choosing flows and methodologies for SoC design (DW, YZ, MSA, MB, CH), p. 167.
DATE-2005-MarinissenPKZ #challenge #design #embedded #memory management
Challenges in Embedded Memory Design and Test (EJM, BP, DKS, YZ), pp. 722–727.
DATE-2005-ZorianFWESGR #industrial #question
Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? (YZ, BF, DW, JE, GS, MG, KNR), p. 572.
DATE-2003-KranitisXGPZ #low cost #self
Low-Cost Software-Based Self-Testing of RISC Processor Cores (NK, GX, DG, AMP, YZ), pp. 10714–10719.
DAC-2002-Zorian #framework
Embedding infrastructure IP for SOC yield improvement (YZ), pp. 709–712.
DATE-2002-KranitisPGZ #effectiveness #self
Effective Software Self-Test Methodology for Processor Cores (NK, AMP, DG, YZ), pp. 592–597.
DATE-2002-PomeranzZ #fault #testing #using
Fault Isolation Using Tests for Non-Isolated Blocks (IP, YZ), p. 1123.
DATE-2001-PaschalisGKPZ #embedded #self
Deterministic software-based self-testing of embedded processor cores (AMP, DG, NK, MP, YZ), pp. 92–96.
DATE-2001-ZorianPTTPDSMR #embedded #tutorial
Embedded tutorial: TRP: integrating embedded test and ATE (YZ, PP, JPT, ICT, CEP, OPD, JS, PM, WR), pp. 34–37.
DAC-2000-ZorianM #design #how #question
System chip test: how will it impact your design? (YZ, EJM), pp. 136–141.
DATE-2000-GizopoulosKPPZ #effectiveness #power management
Effective Low Power BIST for Datapaths (DG, NK, MP, AMP, YZ), p. 757.
DATE-2000-Zorian #embedded #scalability #trade-off
Yield Improvement and Repair Trade-Off for Large Embedded Memories (YZ), pp. 69–70.
DATE-2000-ZorianNMLSV #tutorial
Tutorial Statement (YZ, MN, PM, DYL, CWHS, KV), p. 66.
DATE-1999-NicolaidisZ #online #scalability #testing
Scaling Deeper to Submicron: On-Line Testing to the Rescue (MN, YZ), p. 432–?.
DATE-1999-PaschalisKPGZ #architecture #effectiveness #multi #performance
An Effective BIST Architecture for Fast Multiplier Cores (AMP, NK, MP, DG, YZ), pp. 117–121.
DATE-1999-RenovellPFZ #configuration management #interface #logic #testing
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s (MR, JMP, JF, YZ), pp. 618–622.
System-Chip Test Strategies (YZ), pp. 752–757.
DATE-1998-BogueGJZ #self
Built-In Self-Test with an Alternating Output (TB, MG, HJ, YZ), pp. 180–184.
DATE-1998-MetraRMPPFZSS #novel #testing
Novel Technique for Testing FPGAs (CM, MR, GAM, JMP, SP, JF, YZ, DS, GRS), pp. 89–94.
DATE-1998-RenovellPFZ #approach #configuration management #logic
RAM-Based FPGA’s: A Test Approach for the Configurable Logic (MR, JMP, JF, YZ), pp. 82–88.
EDTC-1997-DuarteNBZ #design #implementation
Fault-secure shifter design: results and implementations (RdOD, MN, HB, YZ), pp. 335–341.
EDTC-1997-DufazaZ #generative #on the #pseudo #sequence #testing
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs (CD, YZ), pp. 69–76.
EDAC-1994-AGZS #functional #testing
Functional Tests for Ring-Address SRAM-type FIFOs (AJvdG, YZ, IS), p. 666.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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