Travelled to:1 × Germany
6 × USA
Collaborated with:S.Borkar V.De J.Tschanz M.(.Pant S.Mitra N.Seifert M.Zhang K.A.Bowman S.Lu S.Narendra A.Keshavarzi C.Wilkerson S.Y.Borkar Y.Ye L.Wei S.M.Burns V.Govindarajulu M.Nicolaidis L.Anghel N.Zergainoh Y.Zorian C.Tokunaga A.Raychowdhury M.M.Khellah J.Kulkarni D.Avresky
Talks about:design (3) microprocessor (2) technolog (2) challeng (2) reliabl (2) perform (2) circuit (2) variat (2) power (2) high (2)
Person: Tanay Karnik
DBLP: Karnik:Tanay
Contributed to:
2013
201220092005200420032002Wrote 7 papers:
- DAC-2013-KarnikPB #power management
- Power management and delivery for high-performance microprocessors (TK, M(P, SB), p. 3.
- DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability
- Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
- DAC-2009-BowmanTWLKDB
- Circuit techniques for dynamic variation tolerance (KAB, JT, CW, SLL, TK, VD, SYB), pp. 4–7.
- DAC-2005-MitraKSZ #challenge #design #fault #logic
- Logic soft errors in sub-65nm technologies design and CAD challenges (SM, TK, NS, MZ), pp. 2–4.
- DAC-2004-BorkarKD #challenge #design #reliability
- Design and reliability challenges in nanometer technologies (SB, TK, VD), p. 75.
- DAC-2003-BorkarKNTKD #architecture #parametricity
- Parameter variations and impact on circuits and microarchitecture (SB, TK, SN, JT, AK, VD), pp. 338–342.
- DAC-2002-KarnikYTWBGDB #optimisation #performance
- Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors (TK, YY, JT, LW, SMB, VG, VD, SB), pp. 486–491.