Travelled to:2 × Germany
3 × France
3 × USA
Collaborated with:D.Sciuto W.Fornaciari C.Brandolese C.Bolchini L.Pomante P.Micheli L.Zampella L.D.Vecchio A.Allara
Talks about:analysi (4) level (4) model (3) base (3) methodolog (2) function (2) network (2) system (2) specif (2) partit (2)
Person: Fabio Salice
DBLP: Salice:Fabio
Contributed to:
2005
200420042003
2003200019981997Wrote 10 papers:
- DATE-2005-BolchiniSSP #reliability #self #specification
- Reliable System Specification for Self-Checking Data-Paths (CB, FS, DS, LP), pp. 1278–1283.
- DAC-2004-BrandoleseFS #design #estimation
- An area estimation methodology for FPGA based designs at systemc-level (CB, WF, FS), pp. 129–132.
- DATE-DF-2004-BrandoleseFSS #analysis #energy #modelling #program transformation #source code
- Analysis and Modeling of Energy Reducing Source Code Transformations (CB, WF, FS, DS), pp. 306–311.
- DATE-2003-BrandoleseFSS #analysis #library
- Library Functions Timing Characterization for Source-Level Analysis (CB, WF, FS, DS), pp. 11132–11133.
- DATE-2003-FornaciariMSZ #clustering #specification #towards #uml
- A First Step Towards Hw/Sw Partitioning of UML Specifications (WF, PM, FS, LZ), pp. 10668–10673.
- SAC-2003-SaliceFVP #architecture #clustering #embedded #multi
- Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures (FS, WF, LDV, LP), pp. 661–665.
- DAC-2000-BrandoleseFSS #energy #estimation
- An instruction-level functionally-based energy estimation model for 32-bits microprocessors (CB, WF, FS, DS), pp. 346–351.
- DATE-1998-AllaraFSS #analysis #profiling
- A Model for System-Level Timed Analysis and Profiling (AA, WF, FS, DS), pp. 204–210.
- DATE-1998-BolchiniSS #analysis #concurrent #detection #fault #network
- Fault Analysis in Networks with Concurrent Error Detection Properties (CB, FS, DS), pp. 957–958.
- EDTC-1997-BolchiniSS #design #network #novel
- A novel methodology for designing TSC networks based on the parity bit code (CB, FS, DS), pp. 440–444.