BibSLEIGH — Donatella

Travelled to:

1 × Spain
10 × France
10 × USA
8 × Germany

Collaborated with:

F.Ferrandi F.Salice W.Fornaciari C.Silvano F.Bruschi C.Bolchini F.Fummi C.Brandolese M.Sami V.Zaccaria R.Zafalon M.D.Santambrogio G.Agosta G.Beltrame G.Buonanno V.Rana E.Macii A.Miele L.Fossati F.Redaelli P.Faverio A.Bona M.Rendine M.Serra A.Tumeo G.Palermo S.Swan F.Ghenassia A.Corna L.Fontana A.A.Nacci F.Perini G.Pelosi L.Pomante M.Chiamenti R.Cordone R.W.Calvo L.Gerli A.Allara A.Balboni C.Costi F.Regazzoni D.Lyonnard C.Pilkington G.Ferrara A.Fin L.Benini G.D.Micheli M.Poncino D.Pagano M.Vuka M.Rabozzi R.Cattaneo A.A.Nacci I.Beretta D.Atienza L.Salvemini M.Bombana P.Cavalloro G.Zaza F.Sironi D.B.Bartolini S.Campanoni F.Cancare H.Hoffmann G.Martin W.Rosenstiel P.Flake J.Srouji M.Branca L.Camerini M.Ceriani M.Monchiero H.Schlebusch G.Smith D.Gajski C.Mielenz C.K.Lennard J.Kunkel

Talks about:

system (16) level (10) base (9) function (7) analysi (6) design (6) embed (6) model (5) architectur (4) methodolog (4)

Person: Donatella Sciuto

DBLP: Sciuto:Donatella

Facilitated 1 volumes:

Contributed to:

2015

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1996

1994

1993

Wrote 39 papers:

DATE-2015-CornaFNS #android #detection: Occupancy detection via iBeacon on Android devices for smart building management (AC, LF, AAN, DS), pp. 629–632.
DATE-2015-PaganoVRCSS #configuration management: Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems (DP, MV, MR, RC, DS, MDS), pp. 920–923.
DAC-2013-NacciRBSBA #algorithm #implementation #synthesis: A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices (AAN, VR, FB, DS, IB, DA), p. 6.
DAC-2012-SironiBCCHSS #adaptation #named #operating system #performance #self: Metronome: operating system level performance management via self-adaptive computing (FS, DBB, SC, FC, HH, DS, MDS), pp. 856–865.
DATE-2012-BolchiniMS #adaptation #approach #architecture #fault #manycore #online: An adaptive approach for online fault management in many-core architectures (CB, AM, DS), pp. 1429–1432.
DATE-2011-BruschiPRS #automaton #performance: An efficient Quantum-Dot Cellular Automata adder (FB, FP, VR, DS), pp. 1220–1223.
DATE-2010-TumeoRPFS #architecture #configuration management #implementation #multi #recognition #reliability: A reconfigurable multiprocessor architecture for a reliable face recognition implementation (AT, FR, GP, FF, DS), pp. 319–322.
DATE-2009-BeltrameFS #design #realtime: A real-time application design methodology for MPSoCs (GB, LF, DS), pp. 767–772.
DATE-2008-RedaelliSS #anti #configuration management #scheduling: Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems (FR, MDS, DS), pp. 519–522.
DATE-2008-TumeoBCCMPFS #multi #realtime: A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications (AT, MB, LC, MC, MM, GP, FF, DS), pp. 1039–1044.
DAC-2007-AgostaBPS #approach #canonical: A Unified Approach to Canonical Form-based Boolean Matching (GA, FB, GP, DS), pp. 841–846.
DATE-2006-BeltrameSSLP #simulation: Exploiting TLM and object introspection for system-level simulation (GB, DS, CS, DL, CP), pp. 100–105.
DATE-2005-BolchiniSSP #reliability #self #specification: Reliable System Specification for Self-Checking Data-Paths (CB, FS, DS, LP), pp. 1278–1283.
ICEIS-v1-2005-FaverioSB #enterprise #implementation #process #using: Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs (PF, DS, GB), pp. 285–292.
DATE-DF-2004-BrandoleseFSS #analysis #energy #modelling #program transformation #source code: Analysis and Modeling of Energy Reducing Source Code Transformations (CB, WF, FS, DS), pp. 306–311.
DATE-v1-2004-SciutoMRSGFS #question: SystemC and SystemVerilog: Where do They Fit? Where are They Going? (DS, GM, WR, SS, FG, PF, JS), pp. 122–129.
DAC-2003-AgostaBS #modelling #static analysis #transaction: Static analysis of transaction-level models (GA, FB, DS), pp. 448–453.
DATE-2003-BrandoleseFSS #analysis #library: Library Functions Timing Characterization for Source-Level Analysis (CB, WF, FS, DS), pp. 11132–11133.
DATE-2003-SchlebuschSSGMLGSK #design #problem #question #transaction: Transaction Based Design: Another Buzzword or the Solution to a Design Problem? (HJS, GS, DS, DG, CM, CKL, FG, SS, JK), pp. 10876–10879.
SAC-2003-SalveminiSSSZZ #architecture #embedded #energy #performance #trade-off: A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems (LS, MS, DS, CS, VZ, RZ), pp. 672–678.
DAC-2002-BonaSSZSZ #clustering #embedded #energy #estimation #optimisation: Energy estimation and optimization of embedded VLIW processors based on instruction clustering (AB, MS, DS, VZ, CS, RZ), pp. 886–891.
DATE-2002-BonaSSZSZ #embedded #estimation #optimisation: An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores (AB, MS, DS, VZ, CS, RZ), p. 1128.
DATE-2002-BruschiCFS #design #fault #simulation: Error Simulation Based on the SystemC Design Description Language (FB, MC, FF, DS), p. 1135.
DATE-2002-FerrandiRS #constraints #functional #theorem proving #using #verification: Functional Verification for SystemC Descriptions Using Constraint Solving (FF, MR, DS), pp. 744–751.
DATE-2001-FerrandiFSFF #behaviour #functional #generative #modelling #testing: Functional test generation for behaviorally sequential models (FF, GF, DS, AF, FF), pp. 403–410.
DATE-2001-SamiSSZZ #embedded: Exploiting data forwarding to reduce the power budget of VLIW embedded processors (MS, DS, CS, VZ, RZ), pp. 252–257.
DAC-2000-BrandoleseFSS #energy #estimation: An instruction-level functionally-based energy estimation model for 32-bits microprocessors (CB, WF, FS, DS), pp. 346–351.
DATE-2000-CordoneFSC #approach #heuristic #performance #problem: An Efficient Heuristic Approach to Solve the Unate Covering Problem (RC, FF, DS, RWC), pp. 364–371.
AdaEurope-1999-FornaciariS #co-evolution #design #embedded: HW/SW Co-design of Embedded Systems (WF, DS), pp. 344–355.
DATE-1999-FerrandiFGS #functional #generative #specification: Symbolic Functional Vector Generation for VHDL Specifications (FF, FF, LG, DS), p. 442–?.
DATE-1999-FornaciariSS #embedded #encoding: Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems (WF, DS, CS), pp. 762–763.
DATE-1998-AllaraFSS #analysis #profiling: A Model for System-Level Timed Analysis and Profiling (AA, WF, FS, DS), pp. 204–210.
DATE-1998-BeniniMSMS #encoding #optimisation: Address Bus Encoding Techniques for System-Level Power Optimization (LB, GDM, DS, EM, CS), pp. 861–866.
DATE-1998-BolchiniSS #analysis #concurrent #detection #fault #network: Fault Analysis in Networks with Concurrent Error Detection Properties (CB, FS, DS), pp. 957–958.
EDTC-1997-BolchiniSS #design #network #novel: A novel methodology for designing TSC networks based on the parity bit code (CB, FS, DS), pp. 440–444.
DAC-1996-FerrandiFMPS #automaton #network #optimisation: Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques (FF, FF, EM, MP, DS), pp. 467–470.
EDAC-1994-BalboniCFS #architecture #array #behaviour: From Behavioral Description to Systolic Array Based Architectures (AB, CC, FF, DS), p. 657.
EDAC-1994-FummiSS #approach #fault #functional #generative #testing: A Functional Approach to Delay Faults Test Generation for Sequential Circuits (FF, DS, MS), pp. 51–57.
SEKE-1993-BombanaBCFSZ #analysis #functional #testing: An Expert Solution to Functional Testability Analysis of VLSI Circuits (MB, GB, PC, FF, DS, GZ), pp. 263–265.