Person: Franc Brglez

DBLP: Brglez:Franc

Contributed to:

2005

2003

2002

2001

1998

1997

1994

1994

1993

1992

1990

1987

1981

Wrote 16 papers:

DAC-2005-LiSB #bound #effectiveness #problem

Effective bounding techniques for solving unate and binate covering problems (XYL, MFMS, FB), pp. 385–390.

SAT-2003-LiSB #effectiveness #performance #satisfiability #using

A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation (XYL, MFMS, FB), pp. 53–68.

SAT-2002-BrglezLS #algorithm #benchmark #metric #satisfiability #testing

The role of a skeptic agent in testing and benchmarking of SAT algorithms (FB, XYL, MFS), p. 13.

DAC-2001-BrglezL #design #distributed

A Universal Client for Distributed Networked Design and Computing (FB, HL), pp. 401–406.

DATE-1998-GhoshKBH #benchmark #equivalence #invariant #metric #synthesis

Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking (DG, NK, FB, JEHI), pp. 656–663.

DAC-1997-LavanaKBK #collaboration #design #execution #internet #paradigm #workflow

Executable Workflows: A Paradigm for Collaborative Design on the Internet (HL, AK, FB, KK), pp. 553–558.

DAC-1994-BhattacharyaDB #optimisation #resource management

Clock Period Optimization During Resource Sharing and Assignment (SB, SD, FB), pp. 195–200.

DAC-1994-BhattacharyaDB94a #analysis #optimisation #performance #specification

Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications (SB, SD, FB), pp. 491–496.

DAC-1994-KuznarBZ #clustering #multi

Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect (RK, FB, BZ), pp. 238–243.

EDAC-1994-RohfleischB #logic #optimisation

Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping (BR, FB), pp. 87–93.

EDAC-1994-ZemvaBKZ #fault

A Functionality Fault Model: Feasibility and Applications (AZ, FB, KK, BZ), pp. 152–158.

DAC-1993-KuznarBK #multi

Cost Minimization of Partitions into Multiple Devices (RK, FB, KK), pp. 315–320.

DAC-1992-SchlichtmannBH #agile

Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping (US, FB, MH), pp. 374–379.

DAC-1990-DeyBK #clustering

Corolla Based Circuit Partitioning and Resynthesis (SD, FB, GK), pp. 607–612.

DAC-1987-SchultzB #fault #simulation

Accelerated Transition Fault Simulation (MHS, FB), pp. 237–243.

DAC-1981-SakauyeLRETSABW #design #set #source code

A set of programs for MOS design (GS, AL, JR, RE, JT, ESYS, EA, FB, PSW), pp. 435–442.