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Travelled to:
1 × France
2 × USA
Collaborated with:
J.Ho C.K.Wong R.J.Lipton S.C.North R.Sedgewick J.Valdes S.Gavrilov A.Glebov S.Rusakov D.Blaauw L.G.Jones
Talks about:
tree (2) rectilinear (1) structur (1) procedur (1) approach (1) steiner (1) problem (1) languag (1) describ (1) circuit (1)

Person: Gopalakrishnan Vijayan

DBLP DBLP: Vijayan:Gopalakrishnan

Contributed to:

ED&TC 19971997
DAC 19891989
DAC 19821982

Wrote 4 papers:

EDTC-1997-GavrilovGRBJV #performance
Fast power loss calculation for digital static CMOS circuits (SG, AG, SR, DB, LGJ, GV), pp. 411–415.
DAC-1989-HoVW #approach #problem
A New Approach to the Rectilinear Steiner Tree Problem (JMH, GV, CKW), pp. 161–166.
DAC-1989-Vijayan #clustering
Min-cost Partitioning on a Tree Structure and Applications (GV), pp. 771–774.
DAC-1982-LiptonNSVV #named
ALI: A procedural language to describe VLSI layouts (RJL, SCN, RS, JV, GV), pp. 467–474.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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