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Travelled to:
1 × France
4 × USA
Collaborated with:
J.Simon S.Gavrilov A.Glebov S.Rusakov D.Blaauw G.Vijayan M.Guruswamy R.L.Maziasz D.Dulitz S.Raman V.Chiluvuri A.Fernandez
Talks about:
system (2) switch (2) simul (2) level (2) delay (2) increment (1) synthesi (1) standard (1) hierarch (1) function (1)

Person: Larry G. Jones

DBLP DBLP: Jones:Larry_G=

Contributed to:

DAC 19971997
ED&TC 19971997
DAC 19921992
DAC 19911991
POPL 19861986

Wrote 5 papers:

DAC-1997-GuruswamyMDRCFJ #automation #layout #library #named #standard #synthesis
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries (MG, RLM, DD, SR, VC, AF, LGJ), pp. 327–332.
EDTC-1997-GavrilovGRBJV #performance
Fast power loss calculation for digital static CMOS circuits (SG, AG, SR, DB, LGJ, GV), pp. 411–415.
DAC-1992-Jones #incremental
Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator (LGJ), pp. 424–427.
DAC-1991-Jones91a #simulation
Accelerating Switch-Level Simulation by Function Caching (LGJ), pp. 211–214.
POPL-1986-JonesS #attribute grammar #design
Hierarchical VLSI Design Systems Based on Attribute Grammars (LGJ, JS), pp. 58–69.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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