Travelled to:1 × China
1 × USA
2 × France
2 × Germany
Collaborated with:X.Li Y.Han L.Zhang Y.Wang S.Pei B.Fu C.Wang Y.Zhang Z.Peng J.Jiang M.Fujita J.Wang T.Lv T.Wang J.Deng Y.Fang Z.Du O.Temam P.Ienne D.Novo Y.Chen C.Wu
Talks about:memori (3) test (3) chip (3) network (2) generat (2) exploit (2) optic (2) error (2) delay (2) dram (2)
Person: Huawei Li
DBLP: Li:Huawei
Contributed to:
2015
2015201420112010
2007Wrote 9 papers:
- DAC-2015-WangH0LL #logic #memory management #named
- ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing (YW, YH, LZ, HL, XL), p. 6.
- DAC-2015-WangHWLL #assembly #memory management #named
- RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory (YW, YH, CW, HL, XL), p. 6.
- DATE-2015-DengFDWLTINLCW #fault #hardware #network
- Retraining-based timing error mitigation for hardware neural networks (JD, YF, ZD, YW, HL, OT, PI, DN, XL, YC, CW), pp. 593–596.
- DATE-2015-ZhangPJLF #fault #self
- Temperature-aware software-based self-testing for delay faults (YZ, ZP, JJ, HL, MF), pp. 423–428.
- DATE-2014-WangLLW0 #design #functional #generative #testing
- Functional test generation guided by steady-state probabilities of abstract design (JW, HL, TL, TW, XL), pp. 1–4.
- DATE-2011-WangZHLL #memory management
- Flex memory: Exploiting and managing abundant off-chip optical bandwidth (YW, LZ, YH, HL, XL), pp. 968–973.
- DATE-2010-FuHLL
- Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs (BF, YH, HL, XL), pp. 933–936.
- DATE-2010-PeiLL #generative #testing
- An on-chip clock generation scheme for faster-than-at-speed delay testing (SP, HL, XL), pp. 1353–1356.
- HCI-AS-2007-ZhangLL #algorithm #fault #random
- A Routing Algorithm for Random Error Tolerance in Network-on-Chip (LZ, HL, XL), pp. 1210–1219.