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Travelled to:
1 × France
2 × USA
Collaborated with:
Y.Shin S.Paik J.Seomun
Talks about:
synthesi (3) high (3) circuit (2) level (2) implement (1) perform (1) voltag (1) suppli (1) regist (1) power (1)

Person: Insup Shin

DBLP DBLP: Shin:Insup

Contributed to:

DAC 20102010
DAC 20092009
DATE 20092009

Wrote 3 papers:

DAC-2010-SeomunSS #implementation #power management #synthesis
Synthesis and implementation of active mode power gating circuits (JS, IS, YS), pp. 487–492.
DAC-2009-ShinPS #synthesis #using
Register allocation for high-level synthesis using dual supply voltages (IS, SP, YS), pp. 937–942.
DATE-2009-PaikSS #named #performance #synthesis
HLS-l: High-level synthesis of high performance latch-based circuits (SP, IS, YS), pp. 1112–1117.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.