Person: Youngsoo Shin

DBLP: Shin:Youngsoo

Contributed to:

2015

2011

2010

2009

2009

2008

2007

2006

2001

2000

1999

Wrote 12 papers:

DATE-2015-ChungSS #identification

Identifying redundant inter-cell margins and its application to reducing routing congestion (WC, SS, YS), pp. 1659–1664.

DAC-2011-KungHSS #optimisation

Thermal signature: a simple yet accurate thermal index for floorplan optimization (JK, IH, SSS, YS), pp. 108–113.

DAC-2010-ChuangKSC #optimisation

Pulsed-latch aware placement for timing-integrity optimization (YLC, SK, YS, YWC), pp. 280–285.

DAC-2010-SeomunSS #implementation #power management #synthesis

Synthesis and implementation of active mode power gating circuits (JS, IS, YS), pp. 487–492.

DAC-2009-ShinPS #synthesis #using

Register allocation for high-level synthesis using dual supply voltages (IS, SP, YS), pp. 937–942.

DATE-2009-PaikSS #named #performance #synthesis

HLS-l: High-level synthesis of high performance latch-based circuits (SP, IS, YS), pp. 1112–1117.

DAC-2008-PaikS #multi #optimisation #standard

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements (SP, YS), pp. 600–605.

DAC-2007-SeomunKS

Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits (JS, JK, YS), pp. 103–106.

DAC-2006-KimSKE #design #physics #power management #standard

Physical design methodology of power gating circuits for standard-cell-based design (HOK, YS, HK, IE), pp. 109–112.

DAC-2001-ShinS #design #power management

Coupling-Driven Bus Design for Low-Power Application-Specific Systems (YS, TS), pp. 750–753.

DAC-2000-ShinKC #analysis #embedded #multi #performance #realtime

Schedulability-driven performance analysis of multiple mode embedded real-time systems (YS, DK, KC), pp. 495–500.

DAC-1999-ShinC #realtime #scheduling

Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems (YS, KC), pp. 134–139.