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Travelled to:
2 × USA
Collaborated with:
D.E.Thomas E.M.Dirkes R.A.Walker J.A.Nestor R.L.Blackburn
Talks about:
workbench (1) architect (1) synthesi (1) system (1) delay (1) decis (1) bind (1)

Person: Jayanth V. Rajan

DBLP DBLP: Rajan:Jayanth_V=

Contributed to:

DAC 19881988
DAC 19851985

Wrote 2 papers:

DAC-1988-ThomasDWRNB #architecture
The System Architect’s Workbench (DET, EMD, RAW, JVR, JAN, RLB), pp. 337–343.
DAC-1985-RajanT #synthesis
Synthesis by delayed binding of decisions (JVR, DET), pp. 367–373.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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