BibSLEIGH — Donald_E

Travelled to:

2 × France
2 × Germany
20 × USA

Collaborated with:

J.M.Paul P.Sawkar R.A.Walker R.J.Cloutier R.L.Blackburn T.J.Kowalski D.P.Siewiorek A.Bobrek J.V.Rajan J.A.Nestor G.W.Leive J.J.Pieper W.E.Dougherty J.K.Adams L.F.Arnstein E.D.Lagnese C.Y.H.III J.E.Nelson B.H.Meyer A.S.Hartman A.S.Cassidy S.N.Peffers P.M.Koenig E.A.Snow A.Mellan F.Karim E.M.Dirkes C.Inacio H.Schmit D.Nagle A.Ryan Y.Tong B.Klass A.C.Parker M.Barbacci L.J.Hafer J.Kim

Talks about:

design (16) system (13) synthesi (8) model (6) base (6) behavior (5) level (5) autom (5) represent (4) technolog (3)

Person: Donald E. Thomas

DBLP: Thomas:Donald_E=

Facilitated 1 volumes:

Contributed to:

2010

2007

2004

2003

2002

2000

1999

1996

1995

1994

1993

1992

1990

1989

1988

1985

1983

1982

1981

1979

1978

1977

Wrote 32 papers:

DATE-2010-MeyerHT #effectiveness: Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs (BHM, ASH, DET), pp. 1596–1601.
DAC-2007-BobrekPT #modelling #resource management: Shared Resource Access Attributes for High-Level Contention Models (AB, JMP, DET), pp. 720–725.
DAC-2004-PieperMPTK #multi #simulation: High level cache simulation for heterogeneous multiprocessors (JJP, AM, JMP, DET, FK), pp. 287–292.
DATE-v2-2004-BobrekPNPT #approach #hybrid #modelling #simulation #using: Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach (AB, JJP, JEN, JMP, DET), pp. 1144–1149.
DAC-2003-PaulBNPT #design #modelling #multi #programmable: Schedulers as model-based design elements in programmable heterogeneous multiprocessors (JMP, AB, JEN, JJP, DET), pp. 408–411.
DATE-2003-CassidyPT #concurrent #design #multi #performance #thread: Layered, Multi-Threaded, High-Level Performance Design (ASC, JMP, DET), pp. 10954–10959.
DATE-2002-PaulT #approach #modelling #virtual machine: A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems (JMP, DET), pp. 522–528.
DAC-2000-DoughertyT #behaviour #design #physics #synthesis: Unifying behavioral synthesis and physical design (WED, DET), pp. 756–761.
DAC-2000-PaulPT #hardware #modelling #virtual machine: A codesign virtual machine for hierarchical, balanced hardware/software system modeling (JMP, SNP, DET), pp. 390–395.
DAC-1999-InacioSNRTTK #benchmark #metric: Vertical Benchmarks for CAD (CI, HS, DN, AR, DET, YT, BK), pp. 408–413.
DAC-1996-AdamsT #design #hardware: The Design of Mixed Hardware/Software Systems (JKA, DET), pp. 515–520.
DAC-1995-SawkarT #clustering #multi: Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs (PS, DET), pp. 201–205.
DAC-1994-ArnsteinT #abstraction #behaviour #synthesis #tool support: The Attributed-Behavior Abstraction and Synthesis Tools (LFA, DET), pp. 557–561.
DAC-1993-CloutierT #pipes and filters #set #synthesis: Synthesis of Pipelined Instruction Set Processors (RJC, DET), pp. 583–588.
DAC-1993-SawkarT #performance: Performance Directed Technology Mapping for Look-Up Table Based FPGAs (PS, DET), pp. 208–212.
DAC-1992-SawkarT #array #programmable: Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays (PS, DET), pp. 368–373.
DAC-1990-CloutierT #algorithm #scheduling: The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm (RJC, DET), pp. 71–76.
DAC-1989-LagneseT #architecture #clustering #design: Architectural Partitioning for System Level Design (EDL, DET), pp. 62–67.
DAC-1988-BlackburnTK #behaviour #design: CORAL II: Linking Behavior and Structure in an IC Design System (RLB, DET, PMK), pp. 529–535.
DAC-1988-ThomasDWRNB #architecture: The System Architect’s Workbench (DET, EMD, RAW, JVR, JAN, RLB), pp. 337–343.
DAC-1985-BlackburnT #behaviour #representation #synthesis: Linking the behavioral and structural dominis of representation in a synthesis system (RLB, DET), pp. 374–380.
DAC-1985-KowalskiT #automation #design #knowledge base #what: The VLSI design automation assistant: what’s in a knowledge base (TJK, DET), pp. 252–258.
DAC-1985-RajanT #synthesis: Synthesis by delayed binding of decisions (JVR, DET), pp. 367–373.
DAC-1985-WalkerT #design #representation #synthesis: A model of design representation and synthesis (RAW, DET), pp. 453–459.
DAC-1983-HitchcockT #automation #synthesis: A method of automatic data path synthesis (CYHI, DET), pp. 484–489.
DAC-1983-KowalskiT #automation #design #prototype #type system: The VLSI Design Automation Assistant: Prototype system (TJK, DET), pp. 479–483.
DAC-1983-WalkerT #behaviour: Behavioral level transformation in the CMU-DA system (RAW, DET), pp. 788–789.
DAC-1982-NestorT #design #implementation #multi #representation #simulation: Defining and implementing a multilevel design representation with simulation applications (JAN, DET), pp. 740–746.
DAC-1981-LeiveT #logic #synthesis: A technology relative Logic Synthesis and Module Selection system (GWL, DET), pp. 479–485.
DAC-1979-ParkerTSBHLK #automation #design: The CMU design automation system: An example of automated data path design (ACP, DET, DPS, MB, LJH, GWL, JK), pp. 73–80.
DAC-1978-SnowST #design #trade-off: A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs (EAS, DPS, DET), pp. 220–226.
DAC-1977-ThomasS #automation #design #performance #verification: Measuring designer performance to verify design automation systems (DET, DPS), pp. 411–418.