Travelled to:4 × USA
Collaborated with:D.Z.Pan B.Yu K.Yuan X.Xu D.Ding C.Hsu
Talks about:lithographi (2) plan (2) awar (2) stencil (1) regular (1) process (1) pattern (1) overlap (1) hotspot (1) generic (1)
Person: Jhih-Rong Gao
DBLP: Gao:Jhih=Rong
Contributed to:
2015201420132011Wrote 4 papers:
- DAC-2015-XuYGHP #named #self
- PARR: pin access planning and regular routing for self-aligned double patterning (XX, BY, JRG, CLH, DZP), p. 6.
- DAC-2014-GaoXYP #named #optimisation #process
- MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction (JRG, XX, BY, DZP), p. 6.
- DAC-2013-YuYGP #named
- E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system (BY, KY, JRG, DZP), p. 7.
- DAC-2011-DingGYP #detection #learning #named
- AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection (DD, JRG, KY, DZP), pp. 795–800.