BibSLEIGH — David_Z

Travelled to:

1 × France
1 × Germany
11 × USA

Collaborated with:

B.Yu A.Chakraborty K.Yuan Y.Ban W.Jang M.Cho J.Gao S.X.Shi S.K.Lim D.Ding A.Rajaram X.Xu R.Puri M.Jung Y.Lin S.Roy Y.Li A.Ramalingam S.I.Ward K.Lucas A.Kumar K.Lu T.Chen T.Luo D.Newmark P.Yu K.A.Campbell P.Vissa D.Chen D.Liu J.Um M.R.Choudhury J.Mitra G.Ganesan D.Wang H.Xiang L.Liebmann C.Hsu J.Yang K.Athikulwongse Y.Lee Y.Zhang H.Huang R.T.Chen A.K.Singh S.R.Nassif M.Orshansky L.Stok J.M.Cohn D.S.Kung D.Sylvester A.Srivastava S.H.Kulkarni

Talks about:

awar (9) lithographi (8) optim (8) router (7) perform (6) analysi (6) high (6) chip (6) framework (5) layout (5)

Person: David Z. Pan

DBLP: Pan:David_Z=

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2003

Wrote 34 papers:

DAC-2015-CampbellVPC #detection #fault #low cost #synthesis: High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths (KAC, PV, DZP, DC), p. 6.
DAC-2015-LinYP #constraints #performance: High performance dummy fill insertion with coupling and uniformity constraints (YL, BY, DZP), p. 6.
DAC-2015-PanLYXL #multi #question: Pushing multiple patterning in sub-10nm: are we ready? (DZP, LL, BY, XX, YL), p. 6.
DAC-2015-RoyLUP #multi #named #optimisation #paradigm #performance: OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions (SR, DL, JU, DZP), p. 6.
DAC-2015-XuYGHP #named #self: PARR: pin access planning and regular routing for self-aligned double patterning (XX, BY, JRG, CLH, DZP), p. 6.
DAC-2014-GaoXYP #named #optimisation #process: MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction (JRG, XX, BY, DZP), p. 6.
DAC-2014-YuP #composition #layout: Layout Decomposition for Quadruple Patterning Lithography and Beyond (BY, DZP), p. 6.
DAC-2013-LiP #framework #modelling: An accurate semi-analytical framework for full-chip TSV-induced stress modeling (YL, DZP), p. 8.
DAC-2013-RoyCPP #parallel #synthesis #towards #trade-off: Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures (SR, MRC, RP, DZP), p. 8.
DAC-2013-YuYGP #named: E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system (BY, KY, JRG, DZP), p. 7.
DAC-2012-JungPL #3d #reliability: Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs (MJ, DZP, SKL), pp. 317–326.
DAC-2012-WardDP #automation #evaluation #learning #named: PADE: a high-performance placer with automatic datapath extraction and evaluation through high dimensional data learning (SIW, DD, DZP), pp. 756–761.
DAC-2011-BanLP #2d #composition #flexibility #framework #layout: Flexible 2D layout decomposition framework for spacer-type double pattering lithography (YB, KL, DZP), pp. 789–794.
DAC-2011-DingGYP #detection #learning #named: AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection (DD, JRG, KY, DZP), pp. 795–800.
DAC-2011-JungMPL #3d #analysis #optimisation #reliability: TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC (MJ, JM, DZP, SKL), pp. 188–193.
DAC-2010-BanP #layout #modelling #optimisation #robust: Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography (YB, DZP), pp. 408–411.
DAC-2010-JangP #design #performance: Application-aware NoC design for efficient SDRAM access (WJ, DZP), pp. 453–456.
DAC-2010-YangALLP #3d #analysis #layout #optimisation: TSV stress aware timing analysis with applications to 3D-IC layout optimization (JSY, KA, YJL, SKL, DZP), pp. 803–806.
DAC-2009-ChakrabortyKP #framework #named #open source #quality: RegPlace: a high quality open-source placement framework for structured ASICs (AC, AK, DZP), pp. 442–447.
DAC-2009-DingZHCP #framework #integration #named #power management: O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration (DD, YZ, HH, RTC, DZP), pp. 264–269.
DAC-2009-JangP: An SDRAM-aware router for Networks-on-Chip (WJ, DZP), pp. 800–805.
DAC-2009-YuanLP: Double patterning lithography friendly detailed routing with redundant via consideration (KY, KL, DZP), pp. 63–66.
DATE-2009-ChakrabortyGRP #analysis #optimisation: Analysis and optimization of NBTI induced clock skew in gated clock trees (AC, GG, AR, DZP), pp. 296–299.
DAC-2008-ChenCP #framework: An integrated nonlinear placement framework with congestion and porosity aware buffer planning (TCC, AC, DZP), pp. 702–707.
DAC-2008-ChoYBP #named #performance #predict: ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction (MC, KY, YB, DZP), pp. 504–509.
DAC-2008-RajaramP #design #robust #synthesis: Robust chip-level clock tree synthesis for SOC designs (AR, DZP), pp. 720–723.
DATE-2008-ChakrabortySP #layout #optimisation: Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices (AC, SXS, DZP), pp. 849–855.
DATE-2008-ShiRWP #analysis #modelling #statistics: Latch Modeling for Statistical Timing Analysis (SXS, AR, DW, DZP), pp. 1136–1141.
DAC-2007-ChoXPP #named: TROY: Track Router with Yield-driven Wire Planning (MC, HX, RP, DZP), pp. 55–58.
DAC-2007-RamalingamSNOP #analysis #composition #modelling #using: Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis (AR, AKS, SRN, MO, DZP), pp. 148–153.
DAC-2006-ChoP #named: BoxRouter: a new global router based on box expansion and progressive ILP (MC, DZP), pp. 373–378.
DAC-2006-LuoNP #design #incremental #performance: A new LP based incremental timing driven placement for high performance designs (TL, DN, DZP), pp. 1115–1120.
DAC-2006-YuSP #modelling #process: Process variation aware OPC with variational lithography modeling (PY, SXS, DZP), pp. 785–790.
DAC-2003-PuriSCKPSSK #performance: Pushing ASIC performance in a power envelope (RP, LS, JMC, DSK, DZP, DS, AS, SHK), pp. 788–793.