Stem lithographi$ (all stems)

34 papers:

DAC-2015-BadrTG #hybrid #synthesis

Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias (YB, AT, PG), p. 6.

DAC-2015-DingCM #self

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography (YD, CCNC, WKM), p. 6.

DAC-2015-OuTC #self

Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography (HCO, KHT, YWC), p. 6.

MoDELS-2015-SandenRGBJVS #composition #design #modelling

Modular model-based supervisory controller design for wafer logistics in lithography machines (BvdS, MAR, MG, TB, JJ, JV, RRHS), pp. 416–425.

DAC-2014-LiuFC #process #self #using

Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process (IJL, SYF, YWC), p. 6.

DAC-2014-YuP #composition #layout

Layout Decomposition for Quadruple Patterning Lithography and Beyond (BY, DZP), p. 6.

DAC-2013-ChienOCKC

Double patterning lithography-aware analog placement (HCCC, HCO, TCC, TYK, YWC), p. 6.

DAC-2013-Du0SSLMW #self

Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography (YD, QM, HS, JS, GLP, AM, MDFW), p. 6.

DAC-2013-FangLC #multi

Stitch-aware routing for multiple e-beam lithography (SYF, IJL, YWC), p. 6.

DAC-2013-KuangY #approach #composition #layout #performance

An efficient layout decomposition approach for triple patterning lithography (JK, EFYY), p. 6.

DAC-2013-LinCLWC #detection #fuzzy #novel

A novel fuzzy matching model for lithography hotspot detection (SYL, JYC, JCL, WYW, SCC), p. 6.

DAC-2013-YuYGP #named

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system (BY, KY, JRG, DZP), p. 7.

DAC-2012-FangCC #algorithm #composition #layout #novel

A novel layout decomposition algorithm for triple patterning lithography (SYF, YWC, WYC), pp. 1185–1190.

DAC-2011-BanLP #2d #composition #flexibility #framework #layout

Flexible 2D layout decomposition framework for spacer-type double pattering lithography (YB, KL, DZP), pp. 789–794.

DAC-2011-DingGYP #detection #learning #named

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection (DD, JRG, KY, DZP), pp. 795–800.

DAC-2011-Singh #challenge

Lithography at 14nm and beyond: choices and challenges (VS), p. 459.

DAC-2010-Agarwal #composition

Frequency domain decomposition of layouts for double dipole lithography (KA), pp. 404–407.

DAC-2010-BanP #layout #modelling #optimisation #robust

Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography (YB, DZP), pp. 408–411.

DAC-2010-LinL #graph

Double patterning lithography aware gridless detailed routing with innovative conflict graph (YHL, YLL), pp. 398–403.

DAC-2009-AbercrombiePC #design #equation #simulation

Use of lithography simulation for the calibration of equation-based design rule checks (DA, FP, CC), pp. 67–70.

DAC-2009-DrmanacLW #predict #process #variability

Predicting variability in nanoscale lithography processes (DGD, FL, LCW), pp. 545–550.

DAC-2009-StrojwasJRP #using

Creating an affordable 22nm node using design-lithography co-optimization (AJS, TJ, VR, LTP), pp. 95–96.

DAC-2009-YuanLP

Double patterning lithography friendly detailed routing with redundant via consideration (KY, KL, DZP), pp. 63–66.

DAC-2009-Zhu #simulation

A parameterized mask model for lithography simulation (ZZ), pp. 963–968.

DATE-2009-SreedharK #analysis #on the

On linewidth-based yield analysis for nanometer lithography (AS, SK), pp. 381–386.

DAC-2008-ChenLC #predict

Predictive formulae for OPC with applications to lithography-friendly routing (TCC, GWL, YWC), pp. 510–515.

DAC-2008-ChoYBP #named #performance #predict

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction (MC, KY, YB, DZP), pp. 504–509.

DATE-2008-SreedharSK #fault #modelling #on the #testing

On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits (AS, AS, SK), pp. 616–621.

DAC-2007-SinghalBSLNC #analysis #modelling #simulation

Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation (RS, AB, ARS, FL, SRN, YC), pp. 823–828.

DAC-2006-CaoDH #standard

Standard cell characterization considering lithography induced variations (KC, SD, JH), pp. 801–804.

DAC-2006-YuSP #modelling #process

Process variation aware OPC with variational lithography modeling (PY, SXS, DZP), pp. 785–790.

DAC-2005-MitraYP #named #performance #simulation #using

RADAR: RET-aware detailed routing using fast lithography simulations (JM, PY, DZP), pp. 369–372.

DAC-1999-KahngP #design

Subwavelength Lithography and Its Potential Impact on Design and EDA (ABK, YCP), pp. 799–804.

DAC-1979-Ozdemir

Electron beam lithography (FSO), pp. 383–391.