Travelled to:1 × Portugal
1 × United Kingdom
2 × USA
Collaborated with:A.Goel S.Krstic C.Tinelli C.Salama G.Malecha W.Taha J.O'Leary A.Fuchs J.Gillenwater A.Y.Zhu
Talks about:verilog (3) synthesiz (2) descript (2) theori (2) static (2) level (2) check (2) type (2) use (2) interconnect (1)
Person: Jim Grundy
DBLP: Grundy:Jim
Contributed to:
2009
200920082007Wrote 4 papers:
- PEPM-2009-SalamaMTGO #consistency #dependent type #using
- Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions (CS, GM, WT, JG, JO), pp. 121–130.
- TACAS-2009-FuchsGGKT #formal method #similarity
- Ground Interpolation for the Theory of Equality (AF, AG, JG, SK, CT), pp. 413–427.
- PEPM-2008-GillenwaterMSZTGO #hardware #static typing #using
- Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability (JG, GM, CS, AYZ, WT, JG, JO), pp. 41–50.
- TACAS-2007-KrsticGGT #parametricity #satisfiability
- Combined Satisfiability Modulo Parametric Theories (SK, AG, JG, CT), pp. 602–617.