BibSLEIGH corpus
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Open Knowledge
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Travelled to:
1 × Spain
2 × USA
Collaborated with:
J.Bengtson C.Salama W.Taha J.Grundy J.O'Leary A.Gehani N.Shankar J.Gillenwater A.Y.Zhu L.Xia Yannick Zakowski Paul He C.Hur B.C.Pierce S.Zdancewic
Talks about:
verilog (3) synthesiz (2) descript (2) static (2) level (2) check (2) autom (2) type (2) use (2) interconnect (1)

Person: Gregory Malecha

DBLP DBLP: Malecha:Gregory

Contributed to:

SAC 20152015
PEPM 20092009
PEPM 20082008
ESOP 20162016
POPL 20202020

Wrote 5 papers:

SAC-2015-MalechaGS #automation
Automated software winnowing (GM, AG, NS), pp. 1504–1511.
PEPM-2009-SalamaMTGO #consistency #dependent type #using
Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions (CS, GM, WT, JG, JO), pp. 121–130.
PEPM-2008-GillenwaterMSZTGO #hardware #static typing #using
Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability (JG, GM, CS, AYZ, WT, JG, JO), pp. 41–50.
ESOP-2016-MalechaB #automation #performance
Extensible and Efficient Automation Through Reflective Tactics (GM, JB), pp. 532–559.
POPL-2020-XiaZHHMPZ #coq #interactive #recursion #representation #source code
Interaction trees: representing recursive and impure programs in Coq (LyX, YZ, PH, CKH, GM, BCP, SZ), p. 32.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.