Travelled to:2 × USA
Collaborated with:W.W.Dai
Talks about:power (2) clock (2) size (2) low (2) distribut (1) process (1) variat (1) insert (1) design (1) buffer (1)
Person: Joe G. Xi
DBLP: Xi:Joe_G=
Contributed to:
19961995Wrote 2 papers:
- DAC-1996-XiD #design #power management
- Useful-Skew Clock Routing With Gate Sizing for Low Power Design (JGX, WWMD), pp. 383–388.
- DAC-1995-XiD #power management #process
- Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution (JGX, WWMD), pp. 491–496.