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Travelled to:
1 × France
7 × USA
Collaborated with:
J.G.Xi M.Sato P.B.Morton W.Sun W.H.II T.Dayan D.Staepelaere R.Kong E.S.Kuh J.Zhao S.Kapur D.E.Long H.Liao R.Wang F.Chang B.Ren A.Wang J.Bakshi K.Liu W.Li
Talks about:
extract (3) base (3) use (3) distribut (2) function (2) process (2) paramet (2) sketch (2) signal (2) rubber (2)

Person: Wayne Wei-Ming Dai

DBLP DBLP: Dai:Wayne_Wei=Ming

Contributed to:

DATE DF 20042004
DAC 20022002
DAC 19981998
DAC 19971997
DAC 19961996
DAC 19951995
DAC 19931993
DAC 19911991
DAC 19871987

Wrote 11 papers:

DATE-DF-2004-RenWBLLD #design
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications (BR, AW, JB, KL, WL, WWMD), pp. 280–285.
DAC-2002-MortonD #estimation
Crosstalk noise estimation for noise management (PBM, WWMD), pp. 659–664.
DAC-1998-ZhaoDKL #3d #performance
Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green’s Functions (JZ, WWMD, SK, DEL), pp. 224–229.
DAC-1997-Dai #verification
Chip Parasitic Extraction and Signal Integrity Verification (WWMD), pp. 717–719.
DAC-1996-SunDH #equation #geometry #independence #parametricity #performance #using
Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance (WS, WWMD, WHI), pp. 371–376.
DAC-1996-XiD #design #power management
Useful-Skew Clock Routing With Gate Sizing for Low Power Design (JGX, WWMD), pp. 383–388.
DAC-1995-XiD #power management #process
Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution (JGX, WWMD), pp. 491–496.
DAC-1993-LiaoDWC #metaprogramming #network #polynomial #using
S-Parameter Based Macro Model of Distributed-Lumped Networks Using Exponentially Decayed Polynomial Function (HL, WWMD, RW, FYC), pp. 726–731.
DAC-1991-DaiDS #generative #sketching
Topological Routing in SURF: Generating a Rubber-Band sketch (WWMD, TD, DS), pp. 39–44.
DAC-1991-DaiKS #sketching
Routability of a Rubber-Band Sketch (WWMD, RK, MS), pp. 45–48.
DAC-1987-DaiSK #layout #performance #representation
A Dynamic and Efficient Representation of Building-Block Layout (WWMD, MS, ESK), pp. 376–384.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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