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Travelled to:
1 × USA
2 × France
2 × Germany
Collaborated with:
D.Marculescu S.Chang C.Hsieh M.Lee
Talks about:
variat (2) consid (2) toler (2) underestim (1) temperatur (1) restructur (1) synthesi (1) sequenti (1) approach (1) schedul (1)

Person: Kai-Chiang Wu

DBLP DBLP: Wu:Kai=Chiang

Contributed to:

DATE 20122012
DATE 20112011
DATE 20102010
DATE 20092009
DAC 20042004

Wrote 5 papers:

DATE-2012-WuLMC #approach #correlation
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms (KCW, MCL, DM, SCC), pp. 1269–1274.
DATE-2011-WuM #analysis #optimisation
Aging-aware timing analysis and optimization considering path sensitization (KCW, DM), pp. 1572–1577.
DATE-2010-WuM #scheduling
Clock skew scheduling for soft-error-tolerant sequential circuits (KCW, DM), pp. 717–722.
DATE-2009-WuM #logic #order #performance
Joint logic restructuring and pin reordering against NBTI-induced performance degradation (KCW, DM), pp. 75–80.
DAC-2004-ChangHW
Re-synthesis for delay variation tolerance (SCC, CTH, KCW), pp. 814–819.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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