Travelled to:1 × France
2 × USA
Collaborated with:T.Kim C.Liu J.Seo
Talks about:techniqu (1) synthesi (1) procedur (1) testabl (1) stepwis (1) schedul (1) circuit (1) voltag (1) static (1) sensit (1)
Person: Ki-Seok Chung
DBLP: Chung:Ki=Seok
Contributed to:
20042001
1994Wrote 3 papers:
- DAC-2004-SeoKC #realtime #scheduling
- Profile-based optimal intra-task voltage scheduling for hard real-time applications (JS, TK, KSC), pp. 87–92.
- DAC-2001-KimCL #estimation #logic
- A Static Estimation Technique of Power Sensitivity in Logic Circuits (TK, KSC, CLL), pp. 215–219.
- EDAC-1994-KimCL #refinement #synthesis #testing
- A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability (TK, KSC, CLL), pp. 586–590.