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Travelled to:
2 × USA
Collaborated with:
Y.Chang H.Ou H.Tsao
Talks about:
capacitor (1) asynchron (1) templat (1) pipelin (1) perform (1) circuit (1) length (1) integr (1) analog (1) ratio (1)

Person: Kuan-Hsien Ho

DBLP DBLP: Ho:Kuan=Hsien

Contributed to:

DAC 20142014
DAC 20132013

Wrote 2 papers:

DAC-2014-HoC #optimisation #performance #pipes and filters
A New Asynchronous Pipeline Template for Power and Performance Optimization (KHH, YWC), p. 6.
DAC-2013-HoOCT #array
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits (KHH, HCO, YWC, HFT), p. 6.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.