Travelled to:1 × Germany
2 × France
3 × USA
Collaborated with:R.Puri T.Kutzschebauch S.Bhattacharya A.J.Sullivan M.A.Iyer W.H.Joyner R.Jammy A.Jerraya J.M.Rabaey W.C.Rhines W.E.Donath P.Kudva P.Villarrubia L.N.Reddy A.Sullivan K.Chakraborty J.M.Cohn D.S.Kung D.Z.Pan D.Sylvester A.Srivastava S.H.Kulkarni
Talks about:decomposit (1) wavefront (1) transform (1) technolog (1) placement (1) synthesi (1) consider (1) challeng (1) perform (1) envelop (1)
Person: Leon Stok
DBLP: Stok:Leon
Facilitated 1 volumes:
EdContributed to:
201020052003
200220001999Wrote 6 papers:
- DAC-2010-PuriJJJRRS #challenge
- EDA challenges and options: investing for the future (RP, WHJ, RJ, AJ, JMR, WCR, LS), pp. 1–2.
- DAC-2005-PuriSB
- Keeping hot chips cool (RP, LS, SB), pp. 285–288.
- DAC-2003-PuriSCKPSSK #performance
- Pushing ASIC performance in a power envelope (RP, LS, JMC, DSK, DZP, DS, AS, SHK), pp. 788–793.
- DATE-2002-KutzschebauchS #composition #layout
- Layout Driven Decomposition with Congestion Consideration (TK, LS), pp. 672–676.
- DATE-2000-DonathKSVRSC #synthesis
- Transformational Placement and Synthesis (WED, PK, LS, PV, LNR, AS, KC), pp. 194–201.
- DATE-1999-StokSI
- Wavefront Technology Mapping (LS, AJS, MAI), p. 531–?.