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Travelled to:
1 × France
Collaborated with:
S.Joshi A.Lombardot E.Beigné S.Girard
Talks about:
methodolog (1) statist (1) complex (1) circuit (1) leakag (1) effici (1) level (1) estim (1) gate (1)

Person: Marc Belleville

DBLP DBLP: Belleville:Marc

Contributed to:

DATE 20132013

Wrote 1 papers:

DATE-2013-JoshiLBBG #estimation #performance #statistics
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits (SJ, AL, MB, EB, SG), pp. 1056–1057.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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