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Travelled to:
2 × Germany
3 × France
Collaborated with:
M.Dessouky H.Aboushady J.Porte F.Pêcheux L.d.Lamarre N.Beilleau A.Kaiser A.Greiner L.Andrade T.Maehne A.Vachoux C.B.Aoun A.Lévêque F.Cenni S.Scotti A.Massouri L.Clavier
Talks about:
synthesi (2) system (2) analog (2) simul (2) sigma (2) modul (2) model (2) delta (2) time (2) precollis (1)

Person: Marie-Minerve Louërat

DBLP DBLP: Lou=euml=rat:Marie=Minerve

Contributed to:

DATE 20152015
DATE 20122012
DATE v1 20042004
DATE 20012001
DATE 20002000

Wrote 5 papers:

DATE-2015-AndradeMVAPL #analysis #data flow #modelling
Pre-simulation symbolic analysis of synchronization issues between discrete event and timed data flow models of computation (LA, TM, AV, CBA, FP, MML), pp. 1671–1676.
DATE-2012-LevequePLACSMC #embedded #feedback #modelling #multi
Holistic modeling of embedded systems with multi-discipline feedback: Application to a Precollision Mitigation Braking System (AL, FP, MML, HA, FC, SS, AM, LC), pp. 739–744.
DATE-v1-2004-AboushadyLBL #automation #simulation #synthesis
Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators (HA, LdL, NB, MML), pp. 674–675.
DATE-2001-DessoukyKLG #case study #design #reuse
Analog design for reuse — case study: very low-voltage sigma-delta modulator (MD, AK, MML, AG), pp. 353–360.
DATE-2000-DessoukyLP #performance #synthesis
Layout-Oriented Synthesis of High Performance Analog Circuits (MD, MML, JP), pp. 53–57.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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