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Travelled to:
1 × France
1 × Germany
2 × USA
Collaborated with:
F.Bruschi P.Cavalloro G.Zaza S.Conigliaro R.B.Hughes G.Musgrave G.Buonanno F.Ferrandi D.Sciuto
Talks about:
synthesi (3) design (2) methodolog (1) function (1) communic (1) testabl (1) exploit (1) circuit (1) analysi (1) system (1)

Person: Massimo Bombana

DBLP DBLP: Bombana:Massimo

Contributed to:

DATE DF 20042004
DATE 20032003
DAC 19951995
SEKE 19931993

Wrote 4 papers:

DATE-DF-2004-BruschiB #communication #design #synthesis
A Design Methodology for the Exploitation of High Level Communication Synthesis (FB, MB), pp. 180–185.
DATE-2003-BombanaB #synthesis
SystemC-VHDL Co-Simulation and Synthesis in the HW Domain (MB, FB), pp. 20101–20105.
DAC-1995-BombanaCCHMZ #case study #synthesis
Design-Flow and Synthesis for ASICs: A Case Study (MB, PC, SC, RBH, GM, GZ), pp. 292–297.
SEKE-1993-BombanaBCFSZ #analysis #functional #testing
An Expert Solution to Functional Testability Analysis of VLSI Circuits (MB, GB, PC, FF, DS, GZ), pp. 263–265.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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