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Travelled to:
5 × USA
Collaborated with:
X.Hu S.Kim R.B.Brown W.J.Condley G.Wilke R.Reis D.Sylvester R.M.Senger E.D.Marsman M.S.McCorquodale F.H.Gebara K.L.Kraver
Talks about:
clock (5) synthesi (2) program (2) buffer (2) reson (2) awar (2) microsystem (1) threshold (1) distribut (1) sequenti (1)

Person: Matthew R. Guthaus

DBLP DBLP: Guthaus:Matthew_R=

Contributed to:

DAC 20122012
DAC 20112011
DAC 20102010
DAC 20062006
DAC 20032003

Wrote 6 papers:

DAC-2012-HuCG #synthesis
Library-aware resonant clock synthesis (LARCS) (XH, WJC, MRG), pp. 145–150.
DAC-2011-HuG #distributed #grid #synthesis
Distributed Resonant clOCK grid Synthesis (ROCKS) (XH, MRG), pp. 516–521.
DAC-2011-KimG #reliability
Leakage-aware redundancy for reliable sub-threshold memories (SK, MRG), pp. 435–440.
DAC-2010-GuthausWR #linear #optimisation #programming
Non-uniform clock mesh optimization with linear programming buffer insertion (MRG, GW, RR), pp. 74–79.
DAC-2006-GuthausSB #programming #using
Clock buffer and wire sizing using sequential programming (MRG, DS, RBB), pp. 1041–1046.
DAC-2003-SengerMMGKGB
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference (RMS, EDM, MSM, FHG, KLK, MRG, RBB), pp. 520–525.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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