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Travelled to:
1 × France
1 × Hungary
1 × Poland
6 × USA
Collaborated with:
S.M.Nowick B.Becker R.Drechsler M.Singh T.Wu R.O.Dror D.E.Shaw O.Grumberg F.Lerda O.Strichman A.Sarabi M.A.Perkowski R.C.Ho M.M.Deneroff J.Gagliardo E.M.Clarke A.Fehnker Z.Han B.H.Krogh O.Stursberg J.P.Grossman J.Kuskin J.A.Bank D.J.Ierardi R.H.Larson U.B.Schafer B.Towles C.Young
Talks about:
system (3) function (2) verif (2) multi (2) logic (2) clock (2) guid (2) base (2) underapproxim (1) counterexampl (1)

Person: Michael Theobald

DBLP DBLP: Theobald:Michael

Contributed to:

ASPLOS 20132013
DAC 20082008
POPL 20052005
DATE v2 20042004
TACAS 20032003
DAC 20012001
DAC 19961996
ICALP 19951995
DAC 19941994

Wrote 9 papers:

ASPLOS-2013-GrossmanKBTDILSTYS #fine-grained #hardware
Hardware support for fine-grained event-driven computation in Anton 2 (JPG, JK, JAB, MT, ROD, DJI, RHL, UBS, BT, CY, DES), pp. 549–560.
DAC-2008-HoTDDGS #identification #logic #verification
Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic (RCH, MT, MMD, ROD, JG, DES), pp. 268–271.
POPL-2005-GrumbergLST #approximate #multi
Proof-guided underapproximation-widening for multi-process systems (OG, FL, OS, MT), pp. 122–131.
DATE-v2-2004-SinghT #architecture #multi
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures (MS, MT), pp. 1008–1013.
TACAS-2003-ClarkeFHKST #abstraction #hybrid #refinement #verification
Verification of Hybrid Systems Based on Counterexample-Guided Abstraction Refinement (EMC, AF, ZH, BHK, OS, MT), pp. 192–207.
DAC-2001-TheobaldN #distributed #optimisation #synthesis
Transformations for the Synthesis and Optimization of Asynchronous Distributed Control (MT, SMN), pp. 263–268.
DAC-1996-TheobaldNW #heuristic #logic #named
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic (MT, SMN, TW), pp. 71–76.
OKFDDs versus OBDDs and OFDDs (BB, RD, MT), pp. 475–486.
DAC-1994-DrechslerSTBP #diagrams #functional #order #performance #representation
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams (RD, AS, MT, BB, MAP), pp. 415–419.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.