BibSLEIGH — Rolf

Travelled to:

1 × Czech Republic
1 × Hungary
1 × Switzerland
1 × The Netherlands
1 × United Kingdom
10 × France
2 × Italy
8 × USA
9 × Germany

Collaborated with:

R.Wille M.Soeken D.Große B.Becker G.Fey H.M.Le U.Kühne W.Günther S.Höreth V.Herdt M.A.Thornton N.Przigoda J.Seiter O.Keszocze N.Drechsler A.Sülflow M.Theobald S.Eggersglüß C.Genz S.Pandey S.Safarpour A.G.Veneris M.Gogolla M.Kuhlmann M.Diepenbeck J.Stoppe F.Haedicke R.Ebendt A.Hett S.Ruppertz T.Ho C.Osewold A.G.Ortiz A.Bernasconi V.Ciriani T.Villa J.Lee J.P.Williams H.M.L.0001 J.Peters C.Hilken J.Peleska C.Braunstein S.Frehse G.W.Dueck F.Rogin T.Klotz S.Rülke H.Hengster H.Schäfer J.Hartmann A.Sarabi M.A.Perkowski J.Oetjens N.Bannow M.Becker O.Bringmann A.Burger M.Chaari S.Chakraborty W.Ecker K.Grüttner T.Kruse C.Kuznik M.Mauderer W.Müller D.Müller-Gritschneder F.Poppen H.Post S.Reiter W.Rosenstiel S.Roth U.Schlichtmann A.v.Schwerin B.Tabacaru A.Viehl

Talks about:

model (11) use (11) base (9) ocl (9) verif (8) uml (8) system (7) design (6) minim (6) synthesi (5)

Person: Rolf Drechsler

DBLP: Drechsler:Rolf

Facilitated 1 volumes:

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2004

2003

2001

1999

1998

1997

1995

1994

2016

Wrote 54 papers:

DAC-2015-HerdtLD #simulation #using #verification: Verifying SystemC using stateful symbolic simulation (VH, HML, RD), p. 6.
DAC-2015-PetersWPKD #constraints #modelling #representation #uml: A generic representation of CCSL time constraints for UML/MARTE models (JP, RW, NP, UK, RD), p. 6.
DATE-2015-StoppeWD #automation #design #locality: Automated feature localization for dynamically generated SystemC designs (JS, RW, RD), pp. 277–280.
MoDELS-2015-PrzigodaHWPD #behaviour #concurrent #modelling #ocl #uml: Checking concurrent behavior in UML/OCL models (NP, CH, RW, JP, RD), pp. 176–185.
TAP-2015-SoekenSD #invariant #ocl #specification: Coverage of OCL Operation Specifications and Invariants (MS, JS, RD), pp. 191–207.
DAC-2014-KeszoczeWHD #synthesis: Exact One-pass Synthesis of Digital Microfluidic Biochips (OK, RW, TYH, RD), p. 6.
DAC-2014-OetjensBBBBCCDEGKKLM0MPPRRRSSTV #challenge #evaluation #prototype #research #safety #state of the art #using: Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges (JHO, NB, MB, OB, AB, MC, SC, RD, WE, KG, TK, CK, HML, MM, WM, DMG, FP, HP, SR, WR, SR, US, AvS, BAT, AV), p. 6.
DATE-2014-LeD #design #towards #verification: Towards verifying determinism of SystemC designs (HML, RD), pp. 1–4.
TAP-2014-DiepenbeckKSD #behaviour #development #testing #verification: Behaviour Driven Development for Tests and Verification (MD, UK, MS, RD), pp. 61–77.
DAC-2013-LeGHD #simulation #using #verification: Verifying SystemC using an intermediate verification language and symbolic simulation (HML, DG, VH, RD), p. 6.
DATE-2013-LeGD #design #fault #locality #scalability: Scalable fault localization for SystemC TLM designs (HML, DG, RD), pp. 35–38.
DATE-2013-SeiterWSD #ocl #specification #uml #verification: Determining relevant model elements for the verification of UML/OCL specifications (JS, RW, MS, RD), pp. 1189–1192.
DATE-2013-WilleGSKD #modelling #towards #verification: Towards a generic verification methodology for system models (RW, MG, MS, MK, RD), pp. 1193–1196.
DATE-2012-HaedickeGD #metric #verification: A guiding coverage metric for formal verification (FH, DG, RD), pp. 617–622.
DATE-2012-SoekenWD #invariant #modelling #ocl #uml: Eliminating invariants in UML/OCL models (MS, RW, RD), pp. 1142–1145.
DATE-2012-WilleDOO #automation #design #power management #synthesis #using: Automatic design of low-power encoders using reversible circuit synthesis (RW, RD, CO, AGO), pp. 1036–1041.
DATE-2012-WilleSD #consistency #debugging #modelling #ocl #uml: Debugging of inconsistent UML/OCL models (RW, MS, RD), pp. 1078–1083.
ICGT-2012-DrechslerDGKLSSW #development: Completeness-Driven Development (RD, MD, DG, UK, HML, JS, MS, RW), pp. 38–50.
TOOLS-EUROPE-2012-SoekenWD #behaviour #development #natural language #using: Assisted Behavior Driven Development Using Natural Language Processing (MS, RW, RD), pp. 269–287.
DATE-2011-EggersglusD #fault #generative #optimisation #pseudo #testing #using: As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization (SE, RD), pp. 1291–1296.
DATE-2011-SoekenWD #aspect-oriented #modelling #uml #verification: Verifying dynamic aspects of UML models (MS, RW, RD), pp. 1077–1082.
DATE-2011-WilleKD #scalability: Determining the minimal number of lines for large reversible circuits (RW, OK, RD), pp. 1204–1207.
TAP-2011-SoekenWD #data type #encoding #modelling #ocl #satisfiability #uml #verification: Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models (MS, RW, RD), pp. 152–170.
DAC-2010-WilleSD: Reducing the number of lines in reversible circuits (RW, MS, RD), pp. 647–652.
DATE-2010-SoekenWKGD #modelling #ocl #satisfiability #uml #using #verification: Verifying UML/OCL models using Boolean satisfiability (MS, RW, MK, MG, RD), pp. 1341–1344.
DAC-2009-FeySD #bound #fault tolerance #using: Computing bounds for fault tolerance using formal techniques (GF, AS, RD), pp. 190–195.
DAC-2009-WilleD #logic #scalability #synthesis: BDD-based synthesis of reversible logic for large functions (RW, RD), pp. 270–275.
DATE-2009-GenzD: Overcoming limitations of the SystemC data introspection (CG, RD), pp. 590–593.
DATE-2009-KuhneGD #analysis #comprehension #design: Property analysis and design understanding (UK, DG, RD), pp. 1246–1249.
DATE-2009-SulflowFBKD #debugging #satisfiability: Increasing the accuracy of SAT-based debugging (AS, GF, CB, UK, RD), pp. 1326–1331.
DATE-2009-WilleGFDD #debugging #network: Debugging of Toffoli networks (RW, DG, SF, GWD, RD), pp. 1284–1289.
DATE-2008-PandeyD #architecture #memory management #optimisation: Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs (SP, RD), pp. 206–211.
DATE-2008-RoginKFDR #automation #design #generative #hardware: Automatic Generation of Complex Properties for Hardware Designs (FR, TK, GF, RD, SR), pp. 545–548.
DATE-2007-GrosseKD #bound #functional #model checking: Estimating functional coverage in bounded model checking (DG, UK, RD), pp. 1176–1181.
DATE-2006-BernasconiCDV #network #performance: Efficient minimization of fully testable 2-SPP networks (AB, VC, RD, TV), pp. 1300–1305.
DATE-2006-FeyGD #verification: Avoiding false negatives in formal verification for protocol-driven blocks (GF, DG, RD), pp. 1225–1226.
DATE-2006-FeySVD #on the #satisfiability: On the relation between simulation-based and SAT-based diagnosis (GF, SS, AGV, RD), pp. 1139–1144.
SFM-2006-DrechslerF #automation #generative: Automatic Test Pattern Generation (RD, GF), pp. 30–55.
DATE-v1-2004-SafarpourVDL #satisfiability: Managing Don’t Cares in Boolean Satisfiability (SS, AGV, RD, JL), pp. 260–265.
DATE-2003-EbendtGD #bound: Combination of Lower Bounds in Exact BDD Minimization (RE, WG, RD), pp. 10758–10763.
DATE-2001-ThorntonD #diagrams #graph transformation #using: Spectral decision diagrams using graph transformations (MAT, RD), pp. 713–719.
DAC-1999-DrechslerG #bound #using: Using Lower Bounds During Dynamic BDD Minimization (RD, WG), pp. 29–32.
DATE-1999-HorethD #specification #verification: Formal Verification of Word-Level Specifications (SH, RD), pp. 52–57.
DATE-1999-ThorntonWDD #diagrams #order #using: Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities (MAT, JPW, RD, ND), pp. 758–759.
DAC-1998-DrechslerDG #performance: Fast Exact Minimization of BDDs (RD, ND, WG), pp. 200–205.
DATE-1998-HorethD #diagrams: Dynamic Minimization of Word-Level Decision Diagrams (SH, RD), pp. 612–617.
EDTC-1997-DrechslerHSHB #testing: Testability of 2-level AND/EXOR circuits (RD, HH, HS, JH, BB), pp. 548–553.
EDTC-1997-HettDB #order #performance #synthesis: Fast and efficient construction of BDDs by reordering based synthesis (AH, RD, BB), pp. 168–175.
TACAS-1997-DrechslerBR #algorithm: Manipulation Algorithms for K*BMDs (RD, BB, SR), pp. 4–18.
ICALP-1995-BeckerDT: OKFDDs versus OBDDs and OFDDs (BB, RD, MT), pp. 475–486.
DAC-1994-DrechslerSTBP #diagrams #functional #order #performance #representation: Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams (RD, AS, MT, BB, MAP), pp. 415–419.
EDAC-1994-BeckerD #diagrams #functional #testing: Testability of Circuits Derived from Functional Decision Diagrams (BB, RD), p. 667.
MoDELS-2016-PrzigodaWD #ocl #performance #smt: Ground setting properties for an efficient translation of OCL in SMT-based model finding (NP, RW, RD), pp. 261–271.
CAV-2016-HerdtLGD #named #performance #simulation: ParCoSS: Efficient Parallelized Compiled Symbolic Simulation (VH, HML0, DG, RD), pp. 177–183.