Travelled to:2 × Germany
3 × France
3 × USA
Collaborated with:K.Mohanram V.Chandra R.C.Aitken A.Zukoski S.Roy R.Puri D.Z.Pan Y.Yoon J.Guo K.Ringgenberg S.Rixner
Talks about:logic (6) circuit (4) error (4) time (4) synthesi (2) reliabl (2) perform (2) driven (2) optim (2) off (2)
Person: Mihir R. Choudhury
DBLP: Choudhury:Mihir_R=
Contributed to:
2013
2011201020092009200820082007Wrote 10 papers:
- DAC-2013-RoyCPP #parallel #synthesis #towards #trade-off
- Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures (SR, MRC, RP, DZP), p. 8.
- DATE-2011-ZukoskiCM #logic #synthesis
- Reliability-driven don’t care assignment for logic synthesis (AZ, MRC, KM), pp. 1560–1565.
- DATE-2010-ChoudhuryCMA #logic #performance
- Analytical model for TDDB-based performance degradation in combinational logic (MRC, VC, KM, RCA), pp. 423–428.
- DATE-2010-ChoudhuryCMA10a #fault #named #online
- TIMBER: Time borrowing and error relaying for online timing error resilience (MRC, VC, KM, RCA), pp. 1554–1559.
- DAC-2009-ChoudhuryM #logic #lookahead #optimisation #using
- Timing-driven optimization using lookahead logic circuits (MRC, KM), pp. 390–395.
- DATE-2009-ChoudhuryM #fault #logic
- Masking timing errors on speed-paths in logic circuits (MRC, KM), pp. 87–92.
- DAC-2008-ChoudhuryYGM
- Technology exploration for graphene nanoribbon FETs (MRC, YY, JG, KM), pp. 272–277.
- DATE-2008-ChoudhuryM #approximate #concurrent #detection #fault #logic
- Approximate logic circuits for low overhead, non-intrusive concurrent error detection (MRC, KM), pp. 903–908.
- DATE-2007-ChoudhuryM #analysis #logic #reliability #scalability
- Accurate and scalable reliability analysis of logic circuits (MRC, KM), pp. 1454–1459.
- DATE-2007-ChoudhuryRRM #interactive #memory management
- Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory (MRC, KR, SR, KM), pp. 1072–1077.