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Travelled to:
2 × USA
3 × Germany
4 × France
Collaborated with:
R.C.Aitken B.H.Calhoun M.R.Choudhury K.Mohanram C.Pietrzyk H.Schmit L.T.Pileggi S.Mitra C.Cher S.M.Mueller J.Boley L.Lai P.Gupta S.Nalam A.Xu S.Sinha G.Yeric B.Cline Y.Cao A.Koorapaty K.Y.Tong C.Patel M.Wieckowski D.Sylvester D.Blaauw S.Idgunji
Talks about:
sram (6) write (4) nanoscal (3) voltag (3) model (3) dynam (3) time (3) methodolog (2) reliabl (2) perform (2)

Person: Vikas Chandra

DBLP DBLP: Chandra:Vikas

Contributed to:

DAC 20142014
DATE 20142014
DATE 20132013
DAC 20122012
DATE 20112011
DATE 20102010
DATE 20092009
DATE v2 20042004
DATE 20032003

Wrote 14 papers:

DAC-2014-Chandra #embedded #monitoring #multi #perspective #reliability
Monitoring Reliability in Embedded Processors — A Multi-layer View (VC), p. 6.
Cross layer resiliency in real world (VC, SM, CYC, SMM), p. 1.
DATE-2013-BoleyCAC #analysis #estimation #performance
Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN (JB, VC, RCA, BHC), pp. 1819–1824.
DATE-2013-LaiCAG #monitoring #named #online
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology (LL, VC, RCA, PG), pp. 282–287.
DAC-2012-SinhaYCCC #design #modelling #predict
Exploring sub-20nm FinFET design with predictive technology models (SS, GY, VC, BC, YC), pp. 283–288.
Analytical model for SRAM dynamic write-ability degradation due to gate oxide breakdown (VC, RCA), pp. 1172–1175.
Dynamic write limited minimum operating voltage for nanoscale SRAMs (SN, VC, RCA, BHC), pp. 467–472.
DATE-2010-ChandraPA #on the
On the efficacy of write-assist techniques in low voltage nanoscale SRAMs (VC, CP, RCA), pp. 345–350.
DATE-2010-ChoudhuryCMA #logic #performance
Analytical model for TDDB-based performance degradation in combinational logic (MRC, VC, KM, RCA), pp. 423–428.
DATE-2010-ChoudhuryCMA10a #fault #named #online
TIMBER: Time borrowing and error relaying for online timing error resilience (MRC, VC, KM, RCA), pp. 1554–1559.
DATE-2010-WieckowskiSBCIPA #analysis #black box
A black box method for stability analysis of arbitrary SRAM cell structures (MW, DS, DB, VC, SI, CP, RCA), pp. 795–800.
DATE-2009-ChandraA #reliability #scalability
Impact of voltage scaling on nanoscale SRAM reliability (VC, RCA), pp. 387–392.
DATE-v2-2004-ChandraXSP #design #performance
An Interconnect Channel Design Methodology for High Performance Integrated Circuits (VC, AX, HS, LTP), pp. 1138–1143.
DATE-2003-KoorapatyCTPPS #architecture #logic #programmable
Heterogeneous Programmable Logic Block Architectures (AK, VC, KYT, CP, LTP, HS), pp. 11118–11119.

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