Travelled to:4 × USA
Collaborated with:C.L.Liu ∅ X.Chen S.Dong
Talks about:sequenti (2) circuit (2) reduct (2) optim (2) scan (2) resynthesi (1) constraint (1) technolog (1) desensit (1) perform (1)
Person: Peichen Pan
DBLP: Pan:Peichen
Contributed to:
1999199619951993Wrote 5 papers:
- DAC-1999-Pan #integration
- Performance-Driven Integration of Retiming and Resynthesis (PP), pp. 243–246.
- DAC-1996-ChenPL #reduction
- Desensitization for Power Reduction in Sequential Circuits (XC, PP, CLL), pp. 795–800.
- DAC-1996-PanL
- Optimal Clock Period FPGA Technology Mapping for Sequential Circuits (PP, CLL), pp. 720–725.
- DAC-1995-PanL
- Partial Scan with Pre-selected Scan Signals (PP, CLL), pp. 189–194.
- DAC-1993-PanDL #constraints #graph #layout #reduction
- Optimal Graph Constraint Reduction for Symbolic Layout Compaction (PP, SkD, CLL), pp. 401–406.