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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
4 × USA
Collaborated with:
C.L.Liu X.Chen S.Dong
Talks about:
sequenti (2) circuit (2) reduct (2) optim (2) scan (2) resynthesi (1) constraint (1) technolog (1) desensit (1) perform (1)

Person: Peichen Pan

DBLP DBLP: Pan:Peichen

Contributed to:

DAC 19991999
DAC 19961996
DAC 19951995
DAC 19931993

Wrote 5 papers:

DAC-1999-Pan #integration
Performance-Driven Integration of Retiming and Resynthesis (PP), pp. 243–246.
DAC-1996-ChenPL #reduction
Desensitization for Power Reduction in Sequential Circuits (XC, PP, CLL), pp. 795–800.
Optimal Clock Period FPGA Technology Mapping for Sequential Circuits (PP, CLL), pp. 720–725.
Partial Scan with Pre-selected Scan Signals (PP, CLL), pp. 189–194.
DAC-1993-PanDL #constraints #graph #layout #reduction
Optimal Graph Constraint Reduction for Symbolic Layout Compaction (PP, SkD, CLL), pp. 401–406.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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