Travelled to:3 × USA
Collaborated with:∅ A.Buyuktosunoglu M.B.Healy K.Kailas V.Puente R.Yu A.Hartstein P.Bose J.H.Moreno K.Bernstein P.Andry J.Cann D.Greenberg W.Haensch M.Ignatowski S.J.Koester J.Magerlein R.Puri A.M.Young
Talks about:chip (2) interconnect (1) roadblock (1) processor (1) bandwidth (1) perspect (1) industri (1) challeng (1) perform (1) storag (1)
Person: Philip G. Emma
DBLP: Emma:Philip_G=
Contributed to:
2014
20072006Wrote 3 papers:
- HPCA-2014-EmmaBHKPYHBM #3d
- 3D stacking of high-performance processors (PGE, AB, MBH, KK, VP, RY, AH, PB, JHM), pp. 500–511.
- DAC-2007-BernsteinACEGHIKMPY #3d #challenge #design
- Interconnects in the Third Dimension: Design Challenges for 3D ICs (KB, PA, JC, PGE, DG, WH, MI, SJK, JM, RP, AMY), pp. 562–567.
- HPCA-2006-Emma #capacity #evolution #industrial
- Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth (PGE), p. 201.