BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
2 × Germany
3 × France
4 × USA
Collaborated with:
T.G.R.v.Leuken T.Henriksson P.Bingley R.Derwig J.Geuzebroek E.A.d.Kock J.P.Vink K.v.Berkel K.O.t.Bosch I.Widya V.D.Zivkovic E.F.Deprettere G.W.Sloof P.Dewilde Z.Lu M.Millberg A.Jantsch A.C.Bruce W.J.M.Smits J.Brunel W.M.Kruijtzer P.Lieverse K.A.Vissers G.Essink W.Kruijtzer J.Stuyt W.Ecker A.Mayer S.Hustin C.Amerijckx S.d.Paoli E.Vaumorin
Talks about:
integr (3) manag (3) flow (3) data (3) infrastructur (2) architectur (2) subsystem (2) framework (2) process (2) system (2)

Person: Pieter van der Wolf

DBLP DBLP: Wolf:Pieter_van_der

Contributed to:

DATE 20132013
DATE 20112011
DATE 20092009
DATE 20082008
DATE 20032003
DAC 20002000
DAC 19911991
DAC 19901990
DAC 19881988

Wrote 12 papers:

DATE-2013-WolfD #composition #integration
Modular SoC integration with subsystems: the audio subsystem case (PvdW, RD), pp. 157–162.
DATE-2011-WolfG #integration #predict
SoC infrastructures for predictable system integration (PvdW, JG), pp. 857–862.
DATE-2009-LuMJBWH #communication
Flow regulation for on-chip communication (ZL, MM, AJ, ACB, PvdW, TH), pp. 578–581.
DATE-2008-KruijtzerWKSEMHAPV #industrial #integration #standard
Industrial IP Integration Flows based on IP-XACT Standards (WK, PvdW, EAdK, JS, WE, AM, SH, CA, SdP, EV), pp. 32–37.
DATE-2008-VinkBW #analysis #architecture #performance
Performance Analysis of SoC Architectures Based on Latency-Rate Servers (JPV, KvB, PvdW), pp. 200–205.
DATE-2008-WolfH #requirements #video
Video Processing Requirements on SoC Infrastructures (PvdW, TH), pp. 1124–1125.
DATE-2003-ZivkovicKWD #architecture #multi #performance #source code
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs (VDZ, EAdK, PvdW, EFD), pp. 10656–10661.
DAC-2000-KockSWBKLVE #modelling #named
YAPI: application modeling for signal processing systems (EAdK, WJMS, PvdW, JYB, WMK, PL, KAV, GE), pp. 402–405.
DAC-1991-BoschBW #design #framework
Design Flow Management in the NELSIS CAD Framework (KOtB, PB, PvdW), pp. 711–716.
DAC-1990-WolfSBD #data transformation #framework
Meta Data Management in the NELSIS CAD Framework (PvdW, GWS, PB, PD), pp. 142–149.
DAC-1988-WidyaLW #concurrent #database #design
Concurrency Control in a VLSI Design Database (IW, TGRvL, PvdW), pp. 357–362.
DAC-1988-WolfL #data transformation #modelling
Object Type Oriented Data Modeling for VLSI Data Management (PvdW, TGRvL), pp. 351–356.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.