BibSLEIGH corpus
BibSLEIGH tags
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BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × France
1 × USA
4 × Germany
Collaborated with:
A.Jantsch S.Liu F.Jafari M.Liu X.Zhao Y.Long X.Yan I.Sander N.Ma Z.Zou L.Zheng X.Chen S.Chen M.H.Yaghmaee W.Kuehn M.Millberg A.C.Bruce P.v.d.Wolf T.Henriksson
Talks about:
chip (5) network (4) switch (4) flow (4) delay (3) no (3) parallel (2) circuit (2) analysi (2) setup (2)

Person: Zhonghai Lu

DBLP DBLP: Lu:Zhonghai

Contributed to:

PDP 20152015
DATE 20142014
DATE 20122012
DATE 20102010
DATE 20092009
DAC 20072007
DATE 20032003

Wrote 12 papers:

PDP-2015-MaZLZ #implementation #mvc
Implementing MVC Decoding on Homogeneous NoCs: Circuit Switching or Wormhole Switching (NM, ZZ, ZL, LRZ), pp. 387–391.
DATE-2014-LiuJL #parallel
Parallel probe based dynamic connection setup in TDM NoCs (SL, AJ, ZL), pp. 1–6.
DATE-2014-LongLY #analysis #bound #evaluation #modelling #multi
Analysis and evaluation of per-flow delay bound for multiplexing models (YL, ZL, XY), pp. 1–4.
DATE-2014-ZhaoL #bound
Empowering study of delay bound tightness with simulated annealing (XZ, ZL), pp. 1–6.
DATE-2012-JafariJL #analysis #scheduling #worst-case
Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling (FJ, AJ, ZL), pp. 538–541.
DATE-2012-LiuJL #constant #parallel
Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC (SL, AJ, ZL), pp. 1289–1294.
DATE-2010-ChenLJC #distributed #manycore #memory management #using
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller (XC, ZL, AJ, SC), pp. 39–44.
Optimal regulation of traffic flows in networks-on-chip (FJ, ZL, AJ, MHY), pp. 1621–1624.
DATE-2010-LiuLKJ #adaptation #correlation #multi
FPGA-based adaptive computing for correlated multi-stream processing (ML, ZL, WK, AJ), pp. 973–976.
DATE-2009-LuMJBWH #communication
Flow regulation for on-chip communication (ZL, MM, AJ, ACB, PvdW, TH), pp. 578–581.
DAC-2007-LuLJ #network
Layered Switching for Networks on Chip (ZL, ML, AJ), pp. 122–127.
DATE-2003-SanderJL #design #development
Development and Application of Design Transformations in ForSyDe (IS, AJ, ZL), pp. 10364–10369.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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