Travelled to:1 × France
1 × USA
Collaborated with:C.Xu D.Niu N.Muralimanohar R.Balasubramonian T.Zhang Y.Xie P.Chen D.Kadetotad Z.Xu A.Mohanty B.Lin J.Ye S.B.K.Vrudhula J.Seo Y.Cao
Talks about:resist (2) architectur (1) technolog (1) algorithm (1) crossbar (1) challeng (1) overcom (1) acceler (1) memori (1) design (1)
Person: Shimeng Yu
DBLP: Yu:Shimeng
Contributed to:
2015
2015Wrote 2 papers:
- DATE-2015-ChenKXMLYVSCY #algorithm #array #learning
- Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip (PYC, DK, ZX, AM, BL, JY, SBKV, JsS, YC, SY), pp. 854–859.
- HPCA-2015-XuNMBZY0 #architecture #challenge #memory management
- Overcoming the challenges of crossbar resistive memory architectures (CX, DN, NM, RB, TZ, SY, YX), pp. 476–488.