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Travelled to:
1 × France
2 × Germany
Collaborated with:
A.Herkersdorf R.Ohlendorf C.Herber A.Richter A.Heinig M.Dietrich F.Miller K.Hahn A.Grunewald R.Brück S.Krohnert J.Reisinger
Talks about:
system (2) more (2) moor (2) use (2) architectur (1) transact (1) ethernet (1) schedul (1) perform (1) gateway (1)

Person: Thomas Wild

DBLP DBLP: Wild:Thomas

Contributed to:

DATE 20152015
DATE 20142014
DATE 20062006

Wrote 3 papers:

DATE-2015-HerberRWH #realtime #scheduling #using
Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling (CH, AR, TW, AH), pp. 61–66.
DATE-2014-HeinigDHMWHGBKR #integration
System integration — The bridge between More than Moore and More Moore (AH, MD, AH, FM, TW, KH, AG, RB, SK, JR), pp. 1–9.
DATE-2006-WildHO #architecture #evaluation #performance #simulation #transaction #using
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation (TW, AH, RO), pp. 248–253.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.