1 × China
1 × USA
Y.Kim O.Mutlu L.Subramanian D.Lee Sridhar Gopinath Nikhil Ghanathe R.S.0001 B.Jaiyen J.Liu G.Pekhimenko S.M.Khan K.K.Chang
dram (4) latenc (3) low (2) architectur (1) predict (1) perform (1) system (1) provid (1) memori (1) machin (1)
Person: Vivek Seshadri
Wrote 4 papers:
- HPCA-2015-LeeKPKSCM #adaptation #optimisation
- Adaptive-latency DRAM: Optimizing DRAM timing for the common-case (DL, YK, GP, SMK, VS, KKWC, OM), pp. 489–501.
- HPCA-2013-LeeKSLSM #architecture #latency #low cost
- Tiered-latency DRAM: A low latency and low cost DRAM architecture (DL, YK, VS, JL, LS, OM), pp. 615–626.
- HPCA-2013-SubramanianSKJM #in memory #memory management #named #performance #predict
- MISE: Providing performance predictability and improving fairness in shared main memory systems (LS, VS, YK, BJ, OM), pp. 639–650.
- PLDI-2019-GopinathGSS #compilation #machine learning #modelling
- Compiling KB-sized machine learning models to tiny IoT devices (SG, NG, VS, RS0), pp. 79–95.