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Travelled to:
1 × China
1 × India
2 × USA
Collaborated with:
O.Mutlu V.Seshadri D.Lee L.Subramanian K.K.Chang D.Han M.Harchol-Balter B.Jaiyen J.Liu G.Pekhimenko S.M.Khan Z.Chishti A.R.Alameldeen C.Wilkerson
Talks about:
dram (5) perform (3) latenc (3) memori (2) improv (2) low (2) architectur (1) algorithm (1) parallel (1) schedul (1)

Person: Yoongu Kim

DBLP DBLP: Kim:Yoongu

Contributed to:

HPCA 20152015
HPCA 20142014
HPCA 20132013
HPCA 20102010

Wrote 5 papers:

HPCA-2015-LeeKPKSCM #adaptation #optimisation
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case (DL, YK, GP, SMK, VS, KKWC, OM), pp. 489–501.
HPCA-2014-ChangLCAWKM #performance
Improving DRAM performance by parallelizing refreshes with accesses (KKWC, DL, ZC, ARA, CW, YK, OM), pp. 356–367.
HPCA-2013-LeeKSLSM #architecture #latency #low cost
Tiered-latency DRAM: A low latency and low cost DRAM architecture (DL, YK, VS, JL, LS, OM), pp. 615–626.
HPCA-2013-SubramanianSKJM #in memory #memory management #named #performance #predict
MISE: Providing performance predictability and improving fairness in shared main memory systems (LS, VS, YK, BJ, OM), pp. 639–650.
HPCA-2010-KimHMH #algorithm #memory management #multi #named #scalability #scheduling
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (YK, DH, OM, MHB), pp. 1–12.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.