BibSLEIGH — Xuehai

Travelled to:

1 × China
2 × USA

Collaborated with:

B.Sahelices Youwei Zhuo J.Torrellas D.Qian Y.Wang Qinyi Luo M.Zhang K.Chen Y.Wu H.Huang Ao Ren Z.Yu Zhendong Bei Caiwen Ding J.Lin X.Lin Xiongchao Tang J.Zhai W.Chen Jiaao He H.Zhang G.Long J.Zhang D.Fan Chengying Huan Teng Ma Zhuo Song Mengxing Liu W.Zheng J.Ren Xingbin Wang R.Hou Boyan Zhao Fengkai Yuan J.Zhang Dan Meng Zhe Li 0001 Q.Qiu Ji Li 0006 Bo Yuan 0001 Ruizhe Cai Ning Liu 0007 Luhao Wang M.Pedram Tianyun Zhang Shaokai Ye Jiayu Li W.Xu Wei Niu Xiaolong Ma S.Lin Shihao Wang B.Ren Xuan Peng X.Shi Hulin Dai H.J.0001 Weiliang Ma Q.Xiong F.Yang

Talks about:

memori (5) architectur (4) high (4) dnn (4) heterogen (3) design (3) base (3) awar (3) implement (2) framework (2)

Person: Xuehai Qian

DBLP: Qian:Xuehai

Contributed to:

2013

2012

2007

2017

2018

2019

2020

Wrote 17 papers:

ASPLOS-2013-QianTSQ #consistency #detection #named #precise #scalability: Volition: scalable and precise sequential consistency violation detection (XQ, JT, BS, DQ), pp. 535–548.
HPCA-2013-QianHSQ #dependence #memory management #named #parallel #performance: Rainbow: Efficient memory dependence recording with high replay parallelism for relaxed memory model (XQ, HH, BS, DQ), pp. 554–565.
HPCA-2012-QianST #design #execution #named #smt: BulkSMT: Designing SMT processors for atomic-block execution (XQ, BS, JT), pp. 153–164.
PDP-2007-QianHZLZF #architecture #design #float #implementation #stack: Design and Implementation of Floating Point Stack on General RISC Architecture (XQ, HH, HZ, GL, JZ, DF), pp. 238–245.
ASPLOS-2017-LiuZCQWZR #memory management #named #persistent #transaction: DudeTM: Building Durable Transactions with Decoupling for Persistent Memory (ML, MZ, KC, XQ, YW, WZ, JR), pp. 329–343.
ASPLOS-2017-RenLDQWLQY #named #network #probability #using: SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing (AR, ZL0, CD, QQ, YW, JL0, XQ, BY0), pp. 405–418.
ASPLOS-2018-CaiRLDWQPW #hardware #named #network: VIBNN: Hardware Acceleration of Bayesian Neural Networks (RC, AR, NL0, CD, LW, XQ, MP, YW), pp. 476–488.
ASPLOS-2018-YuBQ #clustering #in memory: Datasize-Aware High Dimensional Configurations Auto-Tuning of In-Memory Cluster Computing (ZY, ZB, XQ), pp. 564–577.
ASPLOS-2018-ZhangWZQHC #graph #named #novel: Wonderland: A Novel Abstraction-Based Out-Of-Core Graph Processing System (MZ, YW, YZ, XQ, CH, KC), pp. 608–621.
ASPLOS-2019-LuoLZQ #distributed #named: Hop: Heterogeneity-aware Decentralized Training (QL, JL, YZ, XQ), pp. 893–907.
ASPLOS-2019-RenZYLXQLW #co-evolution #design #framework #multi #named #using: ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Methods of Multipliers (AR, TZ, SY, JL, WX, XQ, XL, YW), pp. 925–938.
ASPLOS-2019-TangZQC #architecture #message passing #named #performance: pLock: A Fast Lock for Architectures with Explicit Inter-core Message Passing (XT, JZ, XQ, WC), pp. 765–778.
ASPLOS-2020-LuoHZQ #distributed #named: Prague: High-Performance Heterogeneity-Aware Asynchronous Decentralized Training (QL, JH, YZ, XQ), pp. 401–416.
ASPLOS-2020-MaZCSWQ #architecture #data type #framework #implementation #named #performance #persistent #symmetry: AsymNVM: An Efficient Framework for Implementing Persistent Data Structures on Asymmetric NVM Architecture (TM, MZ, KC, ZS, YW, XQ), pp. 757–773.
ASPLOS-2020-NiuMLWQLWR #execution #mobile #named #realtime: PatDNN: Achieving Real-Time DNN Execution on Mobile Devices with Pattern-based Weight Pruning (WN, XM, SL, SW, XQ, XL, YW, BR), pp. 907–922.
ASPLOS-2020-PengSD0MXYQ #gpu #learning #memory management #named: Capuchin: Tensor-based GPU Memory Management for Deep Learning (XP, XS, HD, HJ0, WM, QX, FY, XQ), pp. 891–905.
ASPLOS-2020-WangHZYZMQ #architecture #named: DNNGuard: An Elastic Heterogeneous DNN Accelerator Architecture against Adversarial Attacks (XW, RH, BZ, FY, JZ, DM, XQ), pp. 19–34.