Streamline verification process with formal property verification to meet highly compressed design cycle
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Prosenjit Chatterjee
Streamline verification process with formal property verification to meet highly compressed design cycle
DAC, 2005.

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@inproceedings{DAC-2005-Chatterjee,
	author        = "Prosenjit Chatterjee",
	booktitle     = "{Proceedings of the 42nd Design Automation Conference}",
	doi           = "10.1145/1065579.1065757",
	isbn          = "1-59593-058-2",
	pages         = "674--677",
	publisher     = "{ACM}",
	title         = "{Streamline verification process with formal property verification to meet highly compressed design cycle}",
	year          = 2005,
}

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