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Travelled to:
1 × France
2 × USA
Collaborated with:
N.Menezes L.T.Pileggi L.T.Pillage R.Panda A.Dharchoudhury G.Vija
Talks about:
circuit (2) optim (2) size (2) interconnect (1) simultan (1) reliabl (1) combin (1) width (1) taper (1) stage (1)

Person: Satyamurthy Pullela

DBLP DBLP: Pullela:Satyamurthy

Contributed to:

DATE 19981998
DAC 19951995
DAC 19931993

Wrote 3 papers:

DATE-1998-PullelaPDV
CMOS Combinational Circuit Sizing by Stage-wise Tapering (SP, RP, AD, GV), pp. 985–986.
DAC-1995-MenezesPP #optimisation
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.
DAC-1993-PullelaMP #optimisation #reliability #using
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization (SP, NM, LTP), pp. 165–170.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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